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PCIe shared memory synchronization

ranchu
Guru 20755 points
Hello, I would like to ask your advice regarding using PCI express shared memory for synchronization: I would like to understand if I can use some flag in shared memory for synchronization between writer-side and reader-side. One side read this flag and can change its value to 1, the other side read and can change its value to 0. Is it possible that when both sides access together (one changes the value, and the other read the value) that then read value will be different then 0 or 1 ? If there are other methods of synchronization I would appreciate any one reference to such methods. Thanks, Ran
  • 0
    Guru 280410 points

    Your synchronization method is valid; the PCIe write posting rules are designed to allow a producer-consumer relationship like yours.
    (Please note that the memory must not be cached.)

    Polling memory to wait for changes eats power, so in practice, this is usually combined with an interrupt (device → host) or a register write (host → device) to tell the other side to wake up.

  • 0 in reply to Clemens Ladisch
    Guru 20755 points
    Hi Clemens, Thank you very much for the reply. I understand from your answers that when the case is writing and reading simultaneously a specific 32 bit register, I can be sure that the operation of read/write is atomic, and the result value of the register is well defined. Many Thanks, Ran
  • 0 in reply to ranchu
    Guru 280410 points

    Individual read or write operations are atomic.

    However, in the general case, when you do a read and then a write, it is possible for someone else to write another value between these two operations.

    In your case, if one side only changes 0 to 1, and the other side only changes 1 to 0, this conflict cannot happen.

  • 0 in reply to Clemens Ladisch
    Guru 20755 points
    Clemens, Just to make it more clear, when you said "individual read or write operations are atomic" , you mean when it is an operation on 32 bit register (not just any block of memory), Right ? Ran
  • 0 in reply to ranchu
    Guru 280410 points

    Yes.

    (Assuming that the device implementing that register isn't buggy.)