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Address Mapping for DDR

Daisuke Maeda
Guru 20425 points

 When REG_IBANK_POS=0 and REG_EBANK_POS=0,

 - What is the maximum number of banks interleaved within a device (per chip select)?
   Is it all the banks?

 - Is the interleaving of banks between the two chip selects possible?

 The current AM335x is only one chip select (DDR_CSn[0])!
 For the current AM335x which setting in the Address Mapping is available?

AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)
http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf
7.3.3.4 Address Mapping
7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0

Best regards,

Daisuke

 

  • 0
    Guru 20425 points

    I want to make the difference between the Address Mappings below clear.

    AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)
    http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf
    7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
    7.3.3.4.2 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 0
    7.3.3.4.3 Address Mapping when REG_IBANK_POS=2 and REG_EBANK_POS = 0
    7.3.3.4.4 Address Mapping when REG_IBANK_POS= 3 and REG_EBANK_POS = 0
    7.3.3.4.5 Address Mapping when REG_IBANK_POS = 0 and REG_EBANK_POS = 1
    7.3.3.4.6 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 1
    7.3.3.4.7 Address Mapping when REG_IBANK_POS = 2 and REG_EBANK_POS = 1
    7.3.3.4.8 Address Mapping when REG_IBANK_POS = 3 and REG_EBANK_POS = 1

    Please refer to the attached file.
    The interleaving is different between the Address Mappings.

    In addition, the TRM describes the case that two chip selects (DDR_CSn[0] and DDR_CSn[1]) are used for.
    But the current AM335x is only one chip select (DDR_CSn[0]).

    Please reply to my question.

    Best regards,

    Daisuke

    1526.AM335x DDR Address Mapping 20120627.xlsx

  • 0 in reply to Daisuke Maeda
    Guru 20425 points

    Please fill the space of the list of my attached file.

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    Guru 20425 points

    I filled the space of the list of my attached file.

    TRM describe "This movement along the banks of the current proceeds to the same page in the next device(if EBANK=1, DDR_CSn[1])".

    It means that the interleaving of banks between the two chip selects is possible when IBANK_POS=0 and EBANK_POS=0.

    TRM describe "Since the DDR2/3/mDDR memory controller interleaves among less number of banks when IBANK_POS!= 0 or EBANK_POS= 1".

    It means that the interleaving of banks within a device (per chip select) is no limited when IBANK_POS=0 and EBANK_POS=0.

    AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)
    http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf
    7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
    7.3.3.4.8 Address Mapping when REG_IBANK_POS = 3 and REG_EBANK_POS = 1

    Best regards,

    Daisuke

    3757.AM335x DDR Address Mapping 20120703.xlsx

     

  • 0 in reply to Daisuke Maeda
    Guru 20425 points

    For the current AM335x which is only one chip select (DDR_CSn[0]), EBANK_POS=1 will be selected!

    Best regards,

    Daisuke