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c6678 cache question

si cheng
Expert 2685 points


hello:

I am working with c6678 evm, I transfer data  from local L2 SRAM to  MSM SRAM with TPCC0, I find that the data  have been transfered  to MSM SRAM, But when I view the  memory, and enable the L1D cache, find that L1D cahce data is differrent with the MSM SRAM. 

<<TMS320C66x DSP Cache User Guide>> says:

C66x DSPs automatically maintain cache coherence for data accesses by the CORE and
EDMA/IDMA through a hardware cache coherence protocol based on snoop
commands. The coherence mechanism is activated on a DMA read and write access.
When a DMA read of a cached L2 SRAM location occurs, the data is directly forwarded
from L1D cache to the DMA without being updated in L2 SRAM. On a DMA write, the
data is forwarded to L1D cache and is updated in L2 SRAM.

so  if I transfer data from local L2 SRAM to MSM SRAM,  the L1D cache data and MSM SRAM data should be the same ,not  different!

I want to know why? thanks!

I load the c6678evm.gel,  and set  Global_Default_Setup(),  witch set L1D 32K Bcache, L1P 32 KB cache, L2 ALL SRAM,  then run my example! 

  • 0
    TI__Intellectual 2415 points

    Hi Cheng,

    In C667x devices, the coherency between external memory (DDR3 or MSMC) and L1D or L2 cache need to be maintained by the programmer (SW). Only the coherency between L2 SRAM and L1D cache is maintained by the C66x CorePAC hardware (L2 to L1D Snoop controller). For more details about maintaining coherency between external memory and L1D or L2 cache, please refer to section 2.4.2.2 "Maintaining Coherence Between External Memory and Cache" of C66x DSP cache users guide, which is available at:

    http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprugy8&fileType=pdf

  • 0 in reply to Karthik Ramana Sankar
    Expert 2685 points

    thanks for your replay!

    you mean default  MSMC  RAM is also external memory? if MSMC RAM is external memory,  I need enable L2 cache,  because  MSMC RAM is cached in L2 cache, and L2 RAM is cached in L1D/L1P. But actually, local L2 SRAM is all sram! and I don't enbale local L2 cache!  

    Is MSMC RAM is cached in L1D defualt?

  • 0 in reply to si cheng
    TI__Intellectual 2415 points

    Yes. MSMC SRAM is considered as external memory. Yes, if L2 cache is not enabled (all L2 is SRAM) then MSMC memory is cached in L1D by default and the coherency between MSMC and L1D cache needs to be maintained by the SW. However, if L2 cache is enabled, then the MSMC memory will get cached in L2 cache and again the coherency between MSMC and L2 cache needs to be maintained by the SW.