I2S LRClock settling time?

Larry Harmon said:

We are using a McBSP as an I2S interface to send data to an audio chip.

The audio chip and the McBSP share the same 8 MHz clock.

The McBSP sample rate generator is configured to divide down the external clock providing the LR clock as wekk as the bit clock.

 

Currently I mm enabling and disabling the clocks before and after I2S transmission.

Lately we have seen (actually heard) some heat related problems.

 

Does the McBSP Sample Rate Generator require a settling time before transmitting data?

I'm not aware of any need for settling time.  The McBSP Sample Rate Generator is a series of dividers.  There is no PLL (Phase Locked Loop) circuit inside that would require some lock time.