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C6748 MARn has what effect after all?

bo shang
Prodigy 120 points

hello.everybody.

      I can not understand the role of MAR C6748 learningprocess.sprufk5a,100 This definition

0184 800Ch       MAR3       Memory Attribute Register 3       0300 0000h - 03FF FFFFh.

So MAR3has what effect after all? 

help me.Thanks.

  • 0
    Expert 1950 points

    Hello,

    The 256 MARn registers control the cacheability of DSP adresse spaces by 16 MBytes blocks (ie 4 GBytes total address range). They are 1 if a particular block is cacheable (0 if not, and 0 at reset). All blocks are not meaningful (for example MAR0..15 would represent internal peripherals).

    Jakez

  • 0 in reply to Jakez
    Prodigy 120 points

    hello,

       L2 Address range 0x0080 0000------0x0083 FFFF,MARn Address range 0x0080 0000--0xFFFFFFFF..What is the difference between the two?

    I can't distinguish between the twoconcepts.please For example.

    Thanks.

  • 0 in reply to bo shang
    Expert 1950 points

    Hello,

    The 16-MByte address range following each MARn register description simply indicates the region whose cacheability is controlled by.

    The MAR0..15, controlling the 0x0000000-0x010000000 regions, are not used.

    The L2 address range 0x00800000 - 0x0083FFFF designates the total 256 KBytes L2 memory space (may be reduced if some is configured as cache).

    In practice, the MARn registers controlling the DDR2 region have to be set, the MARn registers controlling the EMIF CEn are set according to your hardware.

    Jakez

  • 0 in reply to Jakez
    TI__Guru* 84110 points

    Bo Shang,

    Welcome to the embedded processing world of TI DSP. The C6748 is an excellent processor with native floating point instructions and advanced fixed point architecture.

    Your questions are fundamental to an understanding of how to use the C6748. With these questions in mind, it would be very useful for you to work through the online training material for the C6748. This particular understanding of the difference between real memory and control registers will be addressed in the training materials, and there will be many other questions you have not yet asked and those questions will also be answered.

    Please go to the TI Wiki Pages and search for "C6748 workshop" (no quotes). You will find the C6000 Embedded Design Workshop and other training courses there. You will get a lot out of the material if you go through the Student Guide and do each of the labs. The labs and solution files are provided for these courses in addition to the Student Guide.

    Regards,
    RandyP

  • 0 in reply to bo shang
    TI__Guru** 116170 points

    There is  a simple example for understanding of MAR bits and impact of caching in the OMAPL_quickStart_rCSL package. Please download the package from here

    http://processors.wiki.ti.com/index.php/QuickStartOMAPL1x_rCSL

    Please look at the implementation of the CACHE_dspLib_fft example. To understand the performance improvement, the example runs the code with cache disabled and with cache enabled to clearly demonstrate the performance enhancement. This is a low level rCSL based example and provides simple cache APIs to configure the cache.

    Hope this helps.

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Prodigy 120 points

    Thanks,

    I begin to study, do not understand ask you.