regading Antenna Interface Using SFP Connector in TMS320TCI6614 EVM

Hi,

here is the answer of your questions.

1. how is synchronization achieved in SFP Connector because there is no connection between DSP(PHYSYNC,RADSYNC,RP1FBP) and SFP Connector

[AB] SFP connector is only used to transfer link data. all sync pulse and RP01 frame burst is delivered to TI breakout card through AMC port.

you may need this breakout card if you want to connect two EVMs together and you may get more detail from the document in the breakout card box.

2.if we use only SFP Connector (AMC not used) ,how to deal with the PHYSYNC,RADSYNC,RP1FBP.How to achieve synchronisation

[AB] If you use only one EVM with SFP connector, that means you don't want DSP to DSP communication and just want loopback test.

in that case, you may use AIF2 internal loopback mode with SW debug sync (instead of external physync, radsync). if you don't want to use AIF2 internal loopback, you may connect a fiber cable from Tx port to Rx port (it is namely external loopback) and run the same code with SW debug sync option.

3.Our main intention is to connect RRH to SFP Connector(CPRI Interface).(with out AMC Connector)Please suggest on this idea

[AB] Now I understood your plan. in that case, you just can connect the SFP fiber cable to your RRH module directly and start tranferring data from EVM Tx port. however, you stilll need to use SW debug sync register instead of external physync and radsync signal (don't care all external pins except SFP port). then the CPRI frame created by AIF2 will be delivered to your RRH and RRH Rx module should recover the clock from the receiving frame and that same clock should be used to activate Tx module in RRH.   then RRH will start sending UL frames from Antenna with full clock synchronization with TI DSP.  At this time, there must be some time delay between AIF2 and RRH Tx module. AIF2 can adjust this delay by adjusting Ingress AxC offset register in PD module. you may need to read AIF2 UG timing section carefully to understand how you can set AxC offset.   

Regards,

Albert

Hi Albert,

               Thanks for the Reply.We are planning for Custom design board using TMS320TCI6614 DSP where we want to use SFP Connector (for CPRI Interface) and no AMC Connector.We have understood the idea given by you. We just want to make sure that whether your idea is practically implemented so that we can confidently go ahead with our design.( SFP Connector for CPRI Interface without using AMC Connector)

Yes, I confirmed it with RH company in US who normally work with us.

Regards,

Albert

Hi,

     regarding TMDXEVM6614LXE EVM,We have few doubts

1.the PHYSYNC and RADSYNC signals are coming to DSP from CN1 Connector(selecting from DSP_TIM00 or FPGA_FSYNC).but there is also PHYSYNC and RADSYNC signals from AMC.why are the these AMC signals required.finally what PHYSYNC and RADSYNC signals are going to DSP.(they are bit confusing.please clarify.)

2.There are 4 AIF Ports connected from DSP to SFP.may i know whether all these four ports are used for CPRI RRH Interface.also please provide us the SFP Part number details as i unable to find them in BOM.

3.Actually we are planning to connect 6 antenna interface ports from DSP to SFP Connector.Please comment on this idea

Thanks and Regards,

Pradeep N.

Hi Pradeep,

Here is the answers of your questions.

1. if you need to use two EVMs for interconnection test, you may need to use TI breakout card and it requires common phy and rad sync signal from the breakout card through AMC. your main EVM can generate Timer0 output signal and it might be delivered to breakout card by using external cable and that signal comes back to both EVM at the same time through AMC connection,

2. all four ports can be used for CPRI RRH interface. our EVM HW guy is in vacation until next week, so I can not tell you the SFP part number now.

3. it is not possible on our current EVM. you'd better design your own board with six SFP ports. if you need six ports for your RRH, then you may use two EVMs with three SFP port each. in that case, you need to share physync and radsync for both EVM like I explained in answer number 1.

Regards,

Albert