Memory configuration and Cache configuration using .cfg file C6678

Hi Deepu,

QUESTION 1:

There are two parts to this. First you need to define memory sections in your RTSC platform file for your application. You can do this by using the RTSC Platform Wizard in built into CCS. Here's the process:

1. Go to CCS Debug View and Create New RTSC Platform as shown in this snapshot below

2. Select Architecture and Provide Name

3. Default Memory Map that is provided. Check the "Customize Memory" checkbox and edit the memory map as required.

4. For example, in the case of the image processing demo (included in the Multicore Software Development Kit (MCSDK)), the platform is defined as follows:

5. Once you have done this, you will need to point to this platform in your project properties. For example, if we look at the project properties of the image processing demo, you will see this platform is selected under General Properties --> RTSC -> Platform, as the snapshot below indicates. Here you see the platform selected has a platform name "demos.image_processing.ipc.evmc6678l.platform" which was saved in the MCSDK install directory (TI_MCSDK_INSTALL_DIR). So that your platform shows up in the drop-down menu, add the path to your platform by clicking on "Add." Then you will be able to select your platform from the drop-down menu.

6. Now that the platform is defined, you can use the section names that were you defined in the RTSC platform file and refer to them in your .cfg file (aka RTSC configuration). For example, look at the configuration file "image_processing_evmc6678l_master.cfg" in the image processing demo project. You will see that the sections for .bss, .neardata, etc. are defined here and point to the memory sections defined in the RTSC platform file:

.....
Program.sectMap["systemHeapMaster"]     = "DDR3";
Program.sectMap[".cinit"]               = "MSMCSRAM_MASTER";
Program.sectMap[".const"]               = "MSMCSRAM_MASTER";
Program.sectMap[".text"]                = "MSMCSRAM_MASTER";
Program.sectMap[".far"]                 = "L2SRAM";
Program.sectMap[".bss"]                 = "L2SRAM";
Program.sectMap[".rodata"]              = "L2SRAM";
......

QUESTION 2:

L1D, L1P and L2 cache sizes can be set in the RTSC platform as shown in the snapshots above. I believe you can also use the SYS/BIOS Cache module APIs to enable/disable and set sizes. You can look at bios_6_xx_xx_xx\docs\bios6.chm and search for c66 cache.

QUESTION 3:

Looks like a usage error, though not sure. Can you verify usage as below:

Usage for DATA_ALIGN is as "#pragma DATA_ALIGN(pBuffer, 128);"

Usage for DATA_SECTION is as "#pragma DATA_SECTION(pBuffer, "data_buffer");" where you would need to define the section data_buffer" in your .cfg file as Program.sectMap["data_buffer"] = "L2SRAM"; as an example.

Regarding question 3: The syntax that Uday posted above is correct for C.  For C++ (because of how its name mangling works), the variable name is omitted, and the pragmas affect the next symbol that is declared.  For example:

  #pragma DATA_ALIGN(128);

  #pragma DATA_SECTION(".data_buffer");

  int aligned_buffer[2048];

Hi Michael and Uday,

Thanks a lot for the answers. I was able to get around the issues described in Qns 1 & 3.

Regarding question 2, what I was checking was configuring one of the smaller sections defined inside L2 or MSMC as noncache-able. This is not partitioning L2 into L2-CACHE and SRAM. I believe for the external memory, it is possible to do the same by setting the MAR registers(in multiples of 16MBytes sections). Saw a function "Cache_disable( Bits16 type );" among the SYS BIOS cache module APIs, But not sure how to do this.

Pls do let me know, if you have any details regarding this

Thanks

Deepu

Hi Deepu N,

You're right, to make a region of 16MB uncachable, you have to set the corresponding MAR register. The problem is that the MAR controlling the cachability of MSMCSRAM is a read-only register set to 1, (MSMCSRAM is always cachable)

There is a way to make a part of MSMCSRAM uncachable. Using the eXtended Memory Controller (XMC), you can "translate" a block of MSMCSRAM memory to an unused external address, then, set the MAR of this address to "uncachable".

Access to this external address won't use cache, but the access will still lead to MSMCSRAM :)

To translate a block of memory using XMC, you must configure a MPAX.

Here is my own function I used to do it (use CSL) :

void set_MPAX(int index, Uint32 bAddr, Uint32 rAddr, Uint8 segSize){

    CSL_XMC_XMPAXH mpaxh;
    mpaxh.bAddr = bAddr;
    mpaxh.segSize =  segSize;

    CSL_XMC_XMPAXL mpaxl;
    mpaxl.rAddr = rAddr;
    mpaxl.sr = 1;
    mpaxl.sw = 1;
    mpaxl.sx = 1;
    mpaxl.ur = 1;
    mpaxl.uw = 1;
    mpaxl.ux = 1;

    CSL_XMC_setXMPAXH(index, &mpaxh);
    CSL_XMC_setXMPAXL(index, &mpaxl);
}

and here how to use it :

void main(void) {


    CACHE_disableCaching(161); // 161 = 0xa1
    CACHE_setL1PSize(CACHE_L1_32KCACHE);
    CACHE_setL1DSize(CACHE_L1_32KCACHE);
    CACHE_setL2Size(CACHE_0KCACHE);
    set_MPAX(3, 0xa1000, 0x00c3ff, 0xb); // "translate" 4KB (0xb) from 0xa1000000 to 0x00c3ff000 using the MPAX number 3

}

you can read more about XMC and MPAX in the CorePac User's guide : http://www.ti.com/lit/ug/sprugw0b/sprugw0b.pdf

you have to create a section starting a 0xa1000000 and use it to have uncachable MSMCSRAM

in my .cmd file :

MEMORY
{
  L1PSRAM       : o = 0x00e00000, l = 0x00008000
  L1DSRAM      : o = 0x00f00000, l = 0x00008000
  L2SRAM      : o = 0x00800000, l = 0x00080000
  MSMCSRAM       : o = 0x0c000000, l = 0x003FF000 // 4MB - 4KB
  MSMCSRAM_NO_CACHE : o = 0xa1000000, l = 0x00001000 // 4KB
}

SECTIONS
{
  .cinit        : > L2SRAM
  .cio            : > L2SRAM
  .const        : > L2SRAM
  .data            : > L2SRAM
  .far            : > L2SRAM
  .fardata        : > L2SRAM
  .stack        : > L2SRAM
  .sysmem        : > L2SRAM
  .text            : > L2SRAM
  .neardata        : > L2SRAM
  .bss            : > L2SRAM

  .no_cache        : > MSMCSRAM_NO_CACHE
}

So, when I need an uncachable global variable (here, named flag), I write :

#pragma DATA_SECTION(flag,".no_cache");
int flag;

I hope this could help...

regards,

Benoit

Thanks for the reply Benoit.

This answers the query