I am trying to migrate a 6446 to PLL1 of 810 Mhz from 513 MHz (it was at this speed due to legacy code). It is mostly reliable, but I have an eventual lock-up when a lot of ethernet traffic is originating from the device. I have found two clock dividers in the general network area and have scaled them accordingly. These are:
EWINTTCNT - 0x3000 -> 0x4c00
CLKDIV in MDIO CONTROL - 0x4d -> 0x7a.
Beyond this, I've not touched PLL2 (DDR2 @ 135 MHz) and I've made some mods to the NOR-Flash EMIF chip select. That's about it. I'd appreciate it if anybody had any pointers.
Thanks.