hello:
I am using C6678 EDMA, and I want to improve the Performance of EDMA transfer, and the <<EDMA3 Controller User Guide>> 2.12.1.3 TR Pipelining and Data Ordering
says:
TR pipelining refers to the ability of the TC read controller to issue
read commands for a subsequent TR, while the TC write controller is still performing
writes for the previous TR. Consider the case of 2 TRs (TR0 followed by TR1), because
of TR pipelining, the TC read controller can start issuing the read commands for TR1
as soon as the last read command for TR0 has been issued, meanwhile the write
commands and write data for TR0 are tracked by the destination FIFO registers
I want to know How Can I make the the TR pipelining, What need I set before I start a EDMA transfer?
thanks!
