DM8148's C674x internal memory performance issue

Dear Abhishek,

      I am also facing same problem in DDR3 memory access. It will be helpful if you share any update on this.

Thanks

Selvi.

Selvi,

What is the issue that you are seeing w.r.t DDR access? Please describe the issue in more detail.

Dear Renjith,

We are facing more cycle consumption for DDR3 to DDR3 copy. For a 64K DDR3 copy, we get 2,80,800 cycles as peak with cache enabled. Will this much cycles take? Do we miss anything?

Kindly help.

Thanks in advance.

-Selvi

Selvi,

Can you post the function that you are using to do the copy?

Dear Renjith,

We have used memcpy() with known buffers of size 64K in DDR3.

memcpy(&testbuffA, &testbuffB, 16328*4);

Thanks in advance.

-Selvi

Selvi,

I'm not really sure about the exact issue here. But there is some bottleneck w.r.t DDR or Bus access from A8 on DM81xx platforms.

To optimize your code there are two approaches.

1. Try to do word copy instead of byte copy used in memcpy.

2. Try with a newer silicon version. 

Renjith,

Thanks for your suggestions.

To make it clear, we accessing DDR3 from DSP side and not from Arm A8.

Even we tried with 32bit copy instead of single byte copy. The cycles got reduced by 2,10,200.

From where can i relate this problem to silicon revision?

Thanks,

Selvi

Selvi,

There are some issues w.r.t to bus access in DM81xx. AFAIK, it might get fixed in newer silicon revision. However, I cannot guarantee this.

Hi Renjith Thomas , please let me know in which version of DM8148 silicon this problem with DDR access  will be fixed?

ThanX alot

Especially for tests involving L1D and/or L2 memory, make sure that your test code runs entirely from L1P (either configured as memory or as cache), to make sure code fetching time doesn't contaminate to the measurement.

Another interesting test may be copying from DSP internal memory (L1D or L2) to external RAM: since the DSP doesn't wait for completion of writes, this measures purely throughput, while reading from external RAM will also be very sensitive to latency. It did occur to me that the System MMU that's in the DSP MDMA's path most likely will add some latency, even if unused. Using an EDMA transfer to copy data in/out of the DSP internal memories may perform better. Also, when accessing "small stuff" (e.g. L4 peripherals), it's probably preferably to use their mapping on the config port instead of the MDMA port (when applicable).