8148 ARM and DSP shared DDR cache coherency questions

Hi, I'm writing a bare metal system on an 8148 processor using both the DSP and ARM cores. I have some DDR3 connected via the GPMC which both cores have access to and some of which will be used as a shared buffer for data passing between the cores.
I'm focusing on the ARM core at the moment and I have the L2 cache enabled for both Instructions and Data but I am unsure exactly what accesses this will apply to?
I do not have the MMU enabled currently and am just using a flat memory architecture so will the Data caching be applied to all memory accesses through the GPMC? If so does this mean that I could cause cache coherency issues with the DSP and ARM both writing and reading data in the shared area of DDR?

Many Thanks for any help,

Ross