LCD_STAT Sync Loss bit is set

Saleem Shaik

I am working with C6748 processor which is drawing to a 16 bpp TFT display in raster mode. I have set the Master priority registers so that the LCDC has the highest priority i.e 0. I notice that whenever we have to do a very CPU intensive task such as scaling or rotating a set of bitmaps, the SYNC loss bit in the LCD_STAT register gets set. When this happens the rendered image shifts on the screen i.e the origin seems to be someplace in the middle of the screen rather than the bottom left corner.

Any ideas on what can be done to correct this?

Thanks in advance

over 13 years ago

0 JasonHaedt over 13 years ago

Genius 3320 points

More updates on this issue.

We typically see this bit being set in our driver when we have to redraw the entire screen. We are working with a 1024x600 screen with 16Bpp. We have read through the technical manual and it states that this bit occurs if the video buffer is being overwritten or if the BPP setting is modified. We have monitored the beginning of the frame buffer and notice that the palette entries are not modified. The first palette word is 0x40000 followed by 30 bytes of zero. We would be happy to share our raster control settings. The main question still exists, are you able to share detail on what causes the synchronization lost flag on the lcdc controller? The technical manual seems a bit vague.

-Jason

0 Mukul Bhatnagar over 13 years ago

TI__Guru* 84265 points

Jason, Salem

Can you confirm that whatever info provided in the following posts do not help your situation

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/86172.aspx

http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/194298/694390.aspx#694390

Regards

Mukul

0 Mukul Bhatnagar over 13 years ago in reply to Mukul Bhatnagar

TI__Guru* 84265 points

Jason

To eliminate DDR2/mDDR bandwidth bottleneck as the source of this issue I would recommend the following

1) If you are not running the DDR2 at max speed, make sure you try max supported speed 150-156MHz. If you are using max speed, then try reducing the speed to see if the sync lost issue becomes more prominent

2) Make sure that the priority for LCDC is highest, the EDMA TC also have a default priority of 0, so if they are used in the system simultaneously , make sure you are changing the TC priorities to something higher then 0 , to ensure LCDC is truly the highest priority

3) Try to see if tweaking the LCD FIFO threshold alleviates or eliminates the issue

4) Make sure that the DDR BPRIO setting is not at default, if it is , try a value 0x20 instead of default

5) See if moving other competing traffic on DDR to internal RAM (even if it is temp test) makes a difference

If none of the above make any difference then i would strongly suspect a setting/configuration issue or corruption of the LCD configuration as the source of the issue.

Regards

Mukul