C6747 DSP boot issue.
We have a Freescale processor that SPI bootloads the C6747 DSP. The DSP is configured as SPI SLAVE. We had resistors on the config pins, and now are driving them hard, with consistently better results. The processor will sometimes boatload the first time, but mostly takes several attempts to get it to boot.
Our process is as follows:
Power up the rails, with RESET on the DSP
Then set the IO lines to configure the DSP for SPI boot mode
Then release the reset on the DSP
Then initiate communication at 1khz, scale it up to 20MHz
We have looked at all of the timings. It appears that the DSP is properly identifying the boot mode, beginning the boot process, then failing at different points in the process. It does not fail at the same point in the boot process every time.
Is there any documentation that documents the delays and timings for the boot process? It appears that we are on the edge of timing allowances. We have used a logic analyser to look at timing, and it is exactly what we expect to see.
Section 6.5.3 of the datasheet ( SPRS377D ) shows minimum timings but not max times. It seems like we are violating timing, yet we can not determine what/how on our own.
Can there be an IO latchup issue that is creating an issue here, based on our boot up sequence?
Note that we followed the flowchart in the SPRAB04F manual ( Figure 24 ).
Advice on how to debug this will be helpful,
Thanks,
Bryan Busacco
