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C6672 Bootconfig settings for 16-Bit NOR Flash booting

markus desgronte
Prodigy 150 points

Hi,

I have a question concerning the settings of the boot config pins when booting from a NOR Flash which is connected to the EMIF Bus.

Our current setting is the following, hope that this is correct ?

011 11 0 0011 000 1     ( Bootmode Bits 13:0 + Endian Bit)

As shown in the datasheet the Bits 7 to 4 are "Reserved Pins" in an earlier version of the datasheet (SPRS708A—July 2011)   Bit 5 and Bit 4 has been declared as Sub-mode which should be "01" when booting from EMIF16, the latest version of the datasheet now shows that the Sub-mode has been moved to Bit9 and Bit8.

My question now is , what does "Reserved" mean, which values should I use or doesn't it really matter what value these Bits have ?

Thx,

Markus

  • 0
    TI__Mastermind 30825 points

    I'm not sure what DM you're referring to having the EMIF Boot Mode bits 7:4 being reserved (Maybe you meant 7:4 of the DEVSTAT pins since Bootmode[12:0] is the bitfield at DEVSTAT[13:1]. Either way, we'll continue discussing this in terms of bootmode[12:0]

    We did shift the submode from 6:5 to 9:8 in the documentation as we had this incorrectly documented.  Pins 6:3 are still reserved.

    Reserved bit fields normally are do not modify bit fields.  Since this is a captured from the bootstrap pins though, you can set them however you want, it should not impact the operation.  These captured values are used by the BootROM code to determine what to do, so those reserved pins for a specific bootmode are simply ignored.

    It looks to me like you've set it up as Wait Enable - Disabled, and selected a Reserved Submode (i.e. 9:8 you have as 0x11 -> 3 -> Reserved) which isn't a valid sub-mode.

    Bits 12:10 is 011, which is default for a 100MHz Coreclk input to the C6672.  Are you using a 100MHz Coreclk input?

    Here's what I'd recomend for the bootmode pins 011 01 0 0000 000 (does not include endian bit also captured in DEVSTAT register.)

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Prodigy 150 points

    Chad,

    thank you for your quick respond.

    Yes you are correct we are using a 100 MHZ Core clock input.

    Thanks for your answer.

     

    Markus