Hi,
The operation “delay/wait for certain clock cycles” is basic to several L138 operations. For example, in “8.2.2.2 Initializing PLL Mode from PLL Power Down”, one needs to wait for four cycles before PLLC could switch to bypass mode. There is also at least one another place in the TRM where a similar but even longer delay is required.
I checked ARM compile manual SPNU151G, but unfortunately there is no intrinsic designed for this.
So should this be done by inserting a four “NOP” assembly instructions into the code? How to prevent the compiler from optimizing it out?
The ARM compiler manual section 5.8 also show that asm(" assembler text "); can be used to insert assembly code into C program. But in “NOTE: Avoid Disrupting the C/C++ Environment With asm Statements” in the same section, page 89, the last caution is:
“Be especially careful when you use optimization with asm statements. Although the compiler cannot remove asm statements, it can significantly rearrange the code order near them and cause undesired results.”
For the case of waiting “to ensure that the PLLC has switched to bypass mode”, any compiler rearrangement here is unacceptable.
We do believe using as simple as a four-step for loop could achieve the same, but just want a neater solution here.
Paul
