Multiple images in DDR

Tzvi E

Hi,

I want to use single application image for all the 8 cores but because i want to debug the code i need to use the Multiple image method (the image is duplicate in the memory). I can't place all the code and data in L2 because it is too big so i must use the DDR.

The simple way is to generate 8 platform settings and define in each platform the DDR base address and length so there won't be memory overlapping between the cores - the disadvantage of this approach is the needs for 8 different platform files.

I want to use a single cfg with single platform file for all the cores and define in the cfg file the DDR base address and length as dependence of the active core.

For example, if want that each core will use 10MB of DDR (without overlap among the cores) i will use in the cfg file something like this:

var currentExternalMemory = new platform.Memory

currentExternalMemory.base = 0x80000000 + 0x00A00000 * DNUM

currentExternalMemory.len = 0xa00000

Can i do that thing? How?

over 13 years ago

0 Varada Bellary over 13 years ago

TI__Expert 5750 points

If your project is a simple (non-RTSC ) project, then there is an example linker command file.

http://processors.wiki.ti.com/index.php/Linker_CMD_Files_for_CCS

Look for "C6678 Segmented memory model"

Hope this helps. Keep us posted.

0 Tzvi E over 13 years ago in reply to Varada Bellary

Intellectual 450 points

Thanks for your reply.

My project is RTSC project (includes cfg file) - How can i handle my problem in that case?

0 ran35366 over 13 years ago in reply to Tzvi E

TI__Genius 12805 points

Can you explain again why you need multiple images in order to debug your code?

Ran

0 Tzvi E over 13 years ago in reply to ran35366

Intellectual 450 points

Hi,

My application executes the same code on several cores but the data in the cores is different so i need to debug several cores (altgough the code is the same).

0 ran35366 over 13 years ago in reply to Tzvi E

TI__Genius 12805 points

So your problem is how to define separate data memories. Remember that when you use CCSv5 and you have a source window, when you select a core, then the source window refers to the source code of this particular core, so you can debug different cores even if they share the same program image but each core program counter is in a different address.

If my understanding is wrong, let me know.

Now how to define separate data sections? There are several ways:

Using the MPAX registers and translate the SAME logical address to different physical address
Put all the data in a structure and define a vector of structures, and then use the DNUM value to address the structure that belongs to core i
Define multiple data area and use a switch (or if) instruction to give each core a different pointer to the data
I am sure that you can think about other ways

Again, if I miss something in your question, let me know

Ran

0 Tzvi E over 13 years ago in reply to ran35366

Intellectual 450 points

Ran hello,

I want to clarify my question.

If i execute the same application on several cores using single image for all cores - there is a problem to debug/execute the applications because of some problems as can be read in the following link: http://processors.wiki.ti.com/index.php/DSP/BIOS_on_Multi-Core_singleimage

The soultion for this problem is:

1. place all the code and data on L2 (If L2 free space is large enough for code & data)

2. If i must place the Code/Data in DDR memory - Duplicate the application in a way that each core will "see" only part of the DDR and no memory overlap will occured (except of share regions). This solution is mentioned on http://processors.wiki.ti.com/index.php/DSP/BIOS_on_Multi-Core_multipleimage

My question was whether there is a way to have only single RTSC project ond to compile the code so each core will have the same code and data but in different addresses?

Regards,

Jim

0 Tzvi E over 13 years ago in reply to Tzvi E

Intellectual 450 points

Any ideas?

0 Varada Bellary over 13 years ago in reply to Tzvi E

TI__Expert 5750 points

Jim,

Q: My question was whether there is a way to have only single RTSC project ond to compile the code so each core will have the same code and data but in different addresses?

I think the short answer is ‘No’. This cannot be achieved with one single RTSC project. I am going to ask the CCS and RTSC experts to chime in too, for other options.

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Multiple images in DDR