• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 101 subscribers
  • Views 1303 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

some question about the pcie MSI interrupt

liang
Intellectual 290 points
Other Parts Discussed in Thread: TMS320C6678

Hi everyone,

    I am testing the MSI interrupt using the TMS320C6678EVM boards. One operates as RC, and the other one operates as EP. Now I can send MSI interrupt from EP to RC as well as RC to EP. But there are something puzzled me.

   Frist, if I want to used ohter MSI vector such as 1,2....31,what value should I write to MSI_IRQ register.

  Second, what is the relation between the MSI0_IRQ_ENABLE_SET and MSI0_IRQ_ENABLE_CLR? In the test, I found if I set the  MSI0_IRQ_ENABLE_SET, the MSI0_IRQ_ENABLE_CLR haved been set also. and what is the funtion of the two registers?

  Third, whether different device can sent the same vector MSI interrupt to one device?

  Fourth, what is the funtion of the MSI0_IRQ_STATUS register and MSI0_IRQ_STATUS_RAW register? can you explain in detail.

                                                                                                                                                                                                        Thanks.

                                                                                                                                                                                                           LE Liang

    

  • 0
    TI__Genius 12065 points

    1. You should write the vector value into the MSI_IRQ register, such as write 0x1 to trigger MSI vector 1 and write 0x1F to trigger MSI vector 31.

     

    2. As mentioned in the user guide, MSI0_IRQ_ENABLE_SET is write-to-set and MSI0_IRQ_ENABLE_CLR is write-to-clear. You have to write 0x1 to each bit of the MSI0_IRQ_ENABLE_CLR to clear (disable) the MSI vector interrupt.

    Reading of MSI0_IRQ_ENABLE_CLR only reflects the same status of MSI0_IRQ_ENABLE_SET.

     

    3. I think there should be no limitation of multiple devices using the same MSI vector as long you could manage and clean up the interrupt status correctly. But normally different devices trigger different MSI vectors since it is easier to be notified the source of the interrupt.

     

    4. MSI0_IRQ_STATUS_RAW is write-to-set and MSI0_IRQ_STATUS is write-to-clear.

    Write 0x1 to each bit of the MSI0_IRQ_STATUS will clear the status of the MSI interrupt. It should be done before you exit the ISR and make the MSI vector available for the next triggering.

    Writing to MSI0_IRQ_STATUS_RAW is only for debugging purpose. The MSI interrupt status bit is usually being set by the external device which triggers the interrupt in the local device.

    In the debugging, we can also write 0x1 to the bit of the MSI0_IRQ_STATUS_RAW register to trigger the interrupt in the local device by itself.

    Reading of either these two registers should return the current status of each MSI vector interrupt. Normally we could just use MSI0_IRQ_STATUS.

  • 0 in reply to Steven Ji
    Intellectual 290 points

    Hi Steven,

        Thanks very much, I have understand these registers correctly because of you explain. Next I will test that we want to operate one TMS320C6678 as RC  without cpu board and enumerate other device.  We want to run enumerate code on RC without  operating system and enumerate other devices like EP device, FPGA and so on. This is a huge project . Now we have no idea about that, Can you provide some explame .  

  • 0 in reply to liang
    TI__Genius 12065 points

    We do not have PCIe RC driver for C667x. But there is one wiki page talking about the PCIe RC driver of TI81XX, which is using the very similar PCIe module as C667x.

    http://processors.wiki.ti.com/index.php/TI81XX_PCI_Express_Root_Complex_Driver_User_Guide

    You might be able to get an idea of the RC driver development from there. Hope it helps.

  • 0 in reply to Steven Ji
    Intellectual 290 points

    Hi Steven,

        Thanks, I will try it later and tell the result to you. Thanks again!

  • 0 in reply to Steven Ji
    Intellectual 290 points

    Hi Steven,

        It seems to operate with a linux OS. can it operate without a OS?  And the source file and header file located in  "arch/arm/mach-omap2/pcie-ti81xx.c (RC driver source)" "arch/arm/mach-omap2/pcie-ti81xx.h (RC driver private header file)",  I don't know how to find them.

  • 0 in reply to liang
    TI__Genius 12065 points

    Liang,

    The PSP (Platform Support Package) of release 4.0.1.0.6 and above should include the PCIe RC driver source files. I think you can search "DM814x Linux PSP" on ti.com. The PSP could also be found in the following link:

    http://software-dl.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/DM814x_04_01/

  • 0 in reply to Steven Ji
    Intellectual 290 points

    Hi Steven,

        Thanks, I have downloaded the PSP already. 

    Sincerely,

    Liang