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C6672 PCIe outbound read question

UNA
Mastermind 7980 points

Hi

I have a question in the PCIe of C6672.

I can not be accessed normally when I read a byte access in Outbound. Output byte enable(/BE[3:0]) of PCIe-Local bus bridge is not exactly like the following,

1. /BE[3:0] = 0x0 : When lower 4 bit address is 0x0    (All data space (D[31:0) is enable)

2. /BE[3:0] = 0x1 : When lower 4 bit address is 0x1    (Except D[7:0] is enable)

3. /BE[3:0] = 0x3 : When lower 4 bit address is 0x2    (Except D[15:0] is enable)

4. /BE[3:0] = 0x7 : When lower 4 bit address is 0x3    (Except D[31:24] is enable)

I think I would like the following behavior. The byte enable signals of PCIe-Local bus bridge will output a Byte Field of TLP of PCIe. In fact, in the case of using a PCIe device that is not C6672, byte enable output has been successful.

1. /BE[3:0] = 0xE : When lower 4 bit address is 0x0    ( D[7:0] is enable)

2. /BE[3:0] = 0xD : When lower 4 bit address is 0x1    ( D[15:8] is enable)

3. /BE[3:0] = 0x8 : When lower 4 bit address is 0x2    ( D[23:16] is enable)

4. /BE[3:0] = 0x7 : When lower 4 bit address is 0x3    ( D[31:24] is enable)

When the write operation in byte access, the byte enable signals was normal as well.

What will happen like behavior above? and Could you tell me a solution?

Best regards,   Chi

  • 0
    TI__Genius 12065 points

    Chi,

    Could you elaborate more about what you are trying to do please?

    Are you talking about the byte enable field in the TLP header please?

    Are you observing the incorrect output from the PCIe bridge or from the C6672 PCIe please?

    How the C6672 PCIe is configured (RC or EP) and how the PCIe bus bridge is connected to C6672?

    Please let us know how to reproduce the issue you observed. Thanks.

  • 0 in reply to Steven Ji
    Mastermind 7980 points

    Hi, Steven

    Thank you for your reply.  following for more information.

    The C6672 PCIe is configured RC mode and they are connected as follows :

        C6672(RC) ⇔ PCIe Bus bridge  ⇔ FPGA(EP)

    Byte enable field in the TLP header is output from byte enable signal(/BE[3.0]) of PCIe birdge.

    I'm observing the incorrect output from the PCIe bridge,

    When the C6672(RC) read a byte access to the FPGA(EP).

    I think , byte enable field in the TLP header is not correct.

    Best regards, 

    Chi

  • 0 in reply to UNA
    TI__Genius 12065 points

    Chi,

    1. What is the address boundary alignment of the starting address of outbound read please?  I am wondering if anything different if we change the boundary alignment of the access to be larger (like at least 8-byte alignment).

    2. You observed that the output from PCIe bridge is incorrect in the byte enable field. Could you confirm if the output directly from C6672 is correct or not please?

  • 0 in reply to Steven Ji
    Mastermind 7980 points

    Hi, Steven

    I will be described below for your inquiries.

    1. The address boundary alignment is 1-byte, and the starting address is 0x0.    I use EDMA(ACNT=1, BCNT=1) for outbout read. However, both DMA module and host CPU is incorrect(The same result).

       We tried 8-byte alignment, but the output from PCIe bridge is incorrect (/BE[3:0] is 0x0).

     

    2.We can not observe the output from C6672, because we do not have the PCIe protocol analyzer.

     

    Best regards,  

    Chi

  • 0 in reply to UNA
    TI__Genius 12065 points

    Chi,

    May I ask what the ENDIAN configuration is in your setup please?

    We found that if you setup the C66x (local device) in big endian mode and “ENDIAN=2”, which means big endian 4-byte swap, we have to send out more than 2 bytes (16-bit) each time from remote device. Otherwise, the local device could not accept the packets correctly.

     If “ENDIAN=0”, which menas big endian 1-byte swap in C66x, we can send out as few as 1 byte data each time from remote device. The local device could accept 1 byte (8-bit), 2-byte (16-bit) and other data size correctly and swap them for big endian mode in local device.

    Please give a try that if it is the cause of the issue you have seen. Thanks.

  • 0 in reply to Steven Ji
    Mastermind 7980 points

    Steven

     

    I had initially set to "ENDIAN=2".

    So, I tried at "ENDIAN=0". But that did not work correctly (ENDIAN=0 and ENDIAN=2 is same　result.).  

    The write operation is correctly, but the read operation is not correctly.

    What's the difference in the write and read operation ?

     

    Best regards,  

    Chi

  • 0 in reply to UNA
    TI__Genius 12065 points

    Chi,

    Please help me to understand your setup better.

    I could see the PCIe link is as you mentioned before:

    C6672(RC) ⇔ PCIe Bus bridge  ⇔ FPGA(EP)

    And I guess the RC and EP are using different endianess since you setup the ENDIAN=2 originally. But I am not sure if RC is big endian or little endian.

    Could you please give some more info about how the PCIe is configured in both RC and EP, like BAR setup, data rate/lane number, outbound/inbound translation setup?

    Or could you share any example test case that we could reproduce the issue please?