The EMIF Asynchronous Read Operations are generated by EDMA.
The PaRAM configurations are follows.
OPT=0x00100000
SRC=0x62000200
A_B_CNT=0x00012000
DST=0x11800A80
SRC_DST_BIDX=0x00000000
LINK_BCNTRLD=0x0000FFFF
SRC_DST_CIDX=0x00000000
CCNT=1
I have two issues.
- Turnaround period is long!
The TA field in the CEnCFG register is "1", therefore the Turnaround period is 2 cycles.
But the Turnaround period shows 9 cycles.
- The number of Read Operations in the same Chip Select is insufficient!
The TCnDBS field in the CFGCHIP0 register is "2", therefore the DBS is 64 bytes.
The ASIZE field in the CEnCFG register is "1", therefore the Data Bus Width is 16-bit.
Therefore the number of Output Enables in the same Chip Select is 32 times.
But the number of Output Enables shows 16 times.
Please remove my issues.
Best regards,
Daisuke