EVM Gauss c6657 platform - McBSP problem and related onboard FPGA programming

Hi Hari,

The C6657 was designed to accept a TDM interface from the AMC connector such as an AMC T1 card.  This was done to remain compatible with previous EVMs such as the C6472.  You will see in figure 2.13 of the technical reference manual that the frame sync is driven from the AMC connector to the FPGA and distributed to the McBSP_FSR and McBSP_FST.  The clock is distributed from the AMC connector in a similar fashion.  It sounds like you are attempting to drive the frame sync from the C6657.  This isn't valid for the EVM.

Yes in my case, the DSP is programmed to drive FSR out.

On my card, there is not TDM interface connected. I do not have a T1 Card. If so who is driving this FSR? Is there anyway to disable AMC connector -> FGPA to stop driving it. Just treat it as tristate or input pin? I am probing the McBSP signals on the 80 pin header connector. 

Regards,

Hari

The FPGA has a select bit that can tristates the output of the FPGA. The selection between AMC connector and header is done by McBSP_AMC_EN# signal. If this signal is low McBSP is  accessed over AMC edge and FPGA provides the required clocks and frame syncs. If this signal goes high, these clocks and syncs are tri-stated and McBSP is accessed over 80-pin header.  This is described in table 2.7 of the technical reference manual for the EVM.  The McBSP_AMC_EN# bits are found in the miscellaneous register (SPI base + offset 0Ch).  If you set these bits to 11 it will tristate all the McBSP outputs from the FPGA.  The procedure for accessing these registers is described in section 5.5.1. 

Can you point to me which application note you are referring to. Section 5.5.1 and table 2.7. Can you give a link for this document. I am exactly looking for the procedure to write to these registers you mentioned. 0ch. 

Are these registers memory mapped? 

I tried this code: 

/*
* Bit Description Read/Write
1-0 McBSP_AMC_EN#: These bits can be updated by the DSP software to drive values on the McBSP_AMC_EN# pin and for selection of TCLK for McBSP
00: Drive McBSP_AMC_EN# low. Connect TCLKA to McBSP SLCLKs, TxCLKs & RxCLKs. Connect TCLKC to McBSP FSTs & FSRs.
01: Drive McBSP_AMC_EN# low. Connect TCLKB to McBSP SLCLKs, TxCLKs & RxCLKs. (RFU). Connect TCLKC to McBSP FSTs & FSRs.
10: Drive McBSP_AMC_EN# low. Connect TCLKD to McBSP SLCLKs, TxCLKs & RxCLKs. (RFU) Connect TCLKC to McBSP FSTs & FSRs.
11: Drive McBSP_AMC_EN# high. Output SLCLKs, TxCLKs, RxCLKs, FSTs, FSRs as (Hi Z)

*
*/

*((volatile unsigned int *)(0x20BF0000+0x0000000C)) |= 0x00000003;

Thinking that LSB 2 bits if set to b#11 then these pins are tristated. But I am not seeing that happening on my board. Pl. suggest what exactly needs to be here. Any initialization required for SPI? 

The code you've shown above won't work.  The FPGA registers are accesses through the SPI peripheral.  The base address of 0x20BF0000 is the starting address for the control registers for that peripheral.  You will need to configure the SPI interface and use it's control registers to initiate an SPI register access inside the FPGA.  More detail on the SPI can be found in the SPI User's Guide.  I'm checking to see if we have any example code that can be provided to you. 

Note that you have an alpha release of the EVM.  While we strive for perfection on the first release of the board, there may be bugs that hadn't been caught.  I've asked EINFOCHIPS to check the tri-state functionality for the McBSP interface to see if it's working.

Hi Bill,

   I appreciate your help. Could you please forward me the example program to access these registers.

I think default tristate on these pins is desirable. 

Regards,

Hari

Below you will find some example code that should allow you to modify the fpga registers.  Note that this code uses support code available in MDSDK including evmc66x_fpga.c, evmc66x_fpga.h, evmc66x_spi.c and evmc66x_spi.h.

/*
 * main.c
 */
#include <cerrno>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "platform.h"
#include "resource_mgr.h"
#include "evmc665x_fpga.h"

typedef struct test_config {
    uint8_t print_info;
    uint8_t print_current_core_id;
    uint8_t print_switch_state;
    uint8_t test_eeprom;
    uint8_t test_nand;
    uint8_t test_nor;
    uint8_t test_led;
    uint8_t test_uart;
    uint8_t test_external_mem;
    uint8_t test_internal_mem;

    uint32_t init_config_pll1_pllm;
    uint32_t init_config_uart_baudrate;
    uint32_t nand_test_block_number;
    uint32_t nor_test_sector_number;
    uint32_t eeprom_test_slave_address;
    uint32_t led_test_loop_count;
    uint32_t led_test_loop_delay;
    uint32_t ext_mem_test_base_addr;
    uint32_t ext_mem_test_length;
    uint32_t int_mem_test_core_id;
} test_config;

void setup_args(platform_init_flags *flags, test_config *args)
{
        /* should always be 1 */
        flags->pll      =       1;

        /* to init DDR3 */
        flags->ddr      =       1;
        flags->tcsl     =       1;
        flags->phy      =       0;
        flags->ecc      =       0;
        args->print_info        =       1;
        args->print_current_core_id     =       0;
        args->print_switch_state        =       1;
        args->test_eeprom       =       1;
        args->test_nand =       1;
        args->test_nor  =       1;
        args->test_led  =       1;
        args->test_uart =       1;
        args->test_external_mem =       1;
        args->test_internal_mem =       1;

        args->init_config_pll1_pllm = 20;
        args->init_config_uart_baudrate = 19200;
        args->nand_test_block_number    =       510;
        args->nor_test_sector_number    =       10;
        args->eeprom_test_slave_address =       0;
        args->led_test_loop_count       =       1;
        args->led_test_loop_delay       =       2000000;
        args->ext_mem_test_base_addr=   0x80000000;
        args->ext_mem_test_length       =       0x1fffffff;
        args->int_mem_test_core_id      =       1;
}

/* OSAL functions for Platform Library */
uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
{
        return malloc(num_bytes);
}

void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes)
{
    /* Free up the memory */
    if (dataPtr)
    {
        free(dataPtr);
    }
}

void Osal_platformSpiCsEnter(void)
{
    /* Get the hardware semaphore.
     *
     * Acquire Multi core CPPI synchronization lock
     */
    while ((CSL_semAcquireDirect (PLATFORM_SPI_HW_SEM)) == 0);

    return;
}

void Osal_platformSpiCsExit (void)
{
    /* Release the hardware semaphore
     *
     * Release multi-core lock.
     */
    CSL_semReleaseSemaphore (PLATFORM_SPI_HW_SEM);

    return;
}

void main(void)
{

  platform_init_flags  init_flags;
  platform_init_config init_config;
  platform_info        p_info;
  test_config args;

  uint8_t uchValue = 0; /* Default value */
  uint8_t temp;
  uint32_t ret;
  /* Set default values */
  int32_t i,j;

  memset(&args, 0x01, sizeof(test_config));
  memset(&init_flags, 0x01, sizeof(platform_init_flags));

  setup_args(&init_flags, &args);

  init_config.pllm    = args.init_config_pll1_pllm;

 /* if (platform_init(&init_flags, &init_config) != Platform_EOK) {
  printf("Platform failed to initialize, errno = 0x%x \n", platform_errno);
  }*/
  ret = fpgaReadConfigurationRegister(FPGA_DBG_LED_OFFSET, &uchValue);
  ret = fpgaReadConfigurationRegister(0x0C, &uchValue);
  for (j = PLATFORM_USER_LED_CLASS; j < PLATFORM_END_LED_CLASS; j++) {
      for (i = 0; i < 3; i++) {
          platform_write("LED %d ON\n", i);
          platform_led(i, PLATFORM_LED_ON, (LED_CLASS_E)j);
          platform_delay(1000000);
          platform_write("LED %d OFF\n", i);
          platform_led(i, PLATFORM_LED_OFF, (LED_CLASS_E) j);
          platform_delay(1000000);
          platform_write("LED %d ON\n", i);
          platform_led(i, PLATFORM_LED_ON, (LED_CLASS_E)j);
      }
  }

  /*Read FPGA Register*/
  ret = fpgaReadConfigurationRegister(0x0C, &uchValue);
  printf("Register value is %d\n",uchValue);

  /*Write FPGA Register*/
  uchValue = uchValue | 0x03;
  ret = fpgaWriteConfigurationRegister(0x0c, uchValue);

  /*Read back the written values from FPGA Register*/
  fpgaReadConfigurationRegister(0x0C, &uchValue);
  printf("Register value is %d\n",uchValue);

}