Hi,
We tested with PSC for GPIO module, and found that when any pin is configured as output:
1. When PSC is disabled (MDSTAT.STATE = 2, disable), output retain its value
2. When PSC is enabled (MDSTAT.STATE = 3, enable) again, output value remains the same as the last time set, and the same as during disabled states.
So put together GPIO output retains its value across PSC on and off cycle.
“Table 9-3. Module States” says for “Disable”:
This device is designed in full static CMOS, so when you stop a module clock, it retains the module’s state. When the clock is restarted, the module resumes operating from the stopping point.
So when clock is off, GPIO pins configured as input will no longer be effective, and rising/falling edge interrupts would not be captured; but besides these, gating clock off doesn’t affect output states at all. Is this what the design was meant to be?
We are asking this because there are GPIO output pins we use to control on-board peripherals, and we don’t want these peripheral to see value changing on the connected tracks when GPIO PSC is off.
Matt