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OMAP L138 EMIF for 1bit ECC non-CE NAND

Other Parts Discussed in Thread: OMAPL138, AM1808

Hi,

I am trying to interface non-CE 1bit ECC NAND to OMAP L138. According to OMAP L138 datasheet for this type of NAND CS_3 should be used in GPIO mode.

I can access my NAND and able to program it with JTAG using small script which basically programs PSC, PINMUX and GPIO so that CE is pulled low manually.

If this particular piece of code is required to access NAND than how OMAP will boot using this NAND?

Basically it is a chicken-egg problem, i.e. EMIF interface of OMAP needs to programmed first before accessing the code from NAND while the code reside in NAND itself.

Thanks

Pankaj

  • Any one???

    I am having trouble booting up with 1bit ECC NAND. The only option available is to respin the board with 4-bit ECC.

    Also OMAP RBL configures 5 registers CE2CFG, CE3CFG,CE4CFG,CE5CFG,NANDFCR. If i read the default value which is after reset, I can see that EMIFA is configured for 4-bit ECC NAND boot.

    So there should be change in datasheet stating this.

    Thanks

    Pankaj

  • Hi Pankaj

    If I understand you correctly you are using a NAND device (do you have a part number/datasheet to share) that violates the CE requirement listed in the TRM section 2.20l .5.6.4. If that is the case, unfortunately the NAND part cannot be reliably used for booting. While you would be able to read it in user software, by using the GPIO work around, the rom boot loader does not have any comprehension of this GPIO based workaround, and will not incase you want to boot from NAND.

    Regards

    Mukul

  • If you do look for a new NAND device, you might find the following webpage useful

    http://processors.wiki.ti.com/index.php/List_of_NANDs_devices_supported_by_TI_RBLs

    We constantly try to update this page with NANDs that have been tested to work either by us or other users/customers.

    Regards

    Mukul

  • Hi Mukul,

    We are using Hynix HY27US08121B-FPIB NAND flash. As per the list this is not supported and hence we are facing this problem.

    What is CE requirement listed in TRM? Can you please point me to some link for more details?

    For our case, after RBL we read the register value and found that RBL is configuring EMIFA for 4-bit ECC, where as our NAND is 1 bit ECC.

    Also, we want to test our mDDR with debugger. Can you suggest on how to go about it?

    Thanks

    Pankaj

  • Pankaj,

    The CE requirement listed in TRM can found in the EMIFA section which talks about interfacing NAND flash.Refer to section 20.2.5.6.8 for notes on Interfacing to a Non-CE Don't Care NAND Flash with EMIFA.

    As far as the 1 bit ECC spec on your NAND datasheet is concerned, that specification indicates that for normal operation of the NAND, you need at least 1 bit ECC, however the ROM code by default will configure the EMIFA to compute 4 bit ECC which is designed to provide more protection than that is required on the NAND. Most NANDs have enough spare bytes area to store these additional ECC bits so there should be no issue with regards to the ECC requirement of your NAND.

    After the boot is complete if you want to use only 1 bit ECC with your NAND, you can configure the CSnNAND bits in the NANDFCR register to generate 1 bit ECC support. Please refer to the following wiki for FAQ on additional NAND questions.

    http://processors.wiki.ti.com/index.php/Davinci/Sitara/Integra_Nand_Boot_FAQ#I_am_interested_in_using_a_particular_NAND_with_a_TI_device._Will_this_NAND_work.3F

    Regarding your question on mDDR, here are some debugging tips that we have archived  for building platforms which might help:

    http://processors.wiki.ti.com/index.php/OMAP-L138_Hardware_Design_Guide#Testing.2FDebugging

    Regards,

    Rahul

  • Dear Rahul,

    From you statement mention below.

    however the ROM code by default will configure the EMIFA to compute 4 bit ECC which is designed to provide more protection than that is required on the NAND.

    From the document  processors.wiki.ti.com/.../Integra_Nand_Boot_FAQ

    In "What is the ECC support on DM/OMAPL13x/C678x?" section

    It is mentioned that There is no software ECC generation in ROM Bootloader (RBL) in these devices as it is generated using the EMIF hardware

    Whether both statements are conflicting?

    Can you tell me the ECC required for booting from NAND in OMAPL13x or AM180x


    Regards

    Jithin

  • Hi Jithin,

    The ROM code only reads from the NAND so there is no ECC generation involved in reads, there is only ECC based correction so both the statements are correct and not conflicting. The boot ROM code for OMAPL138 and AM1808 supports upto 4 bit ECC based correction (during NAND reads) but when you write to the NAND, you dont need to compute the ECC in software, you can simply configure the EMIFA to set it to generate ECC bits while doing NAND writes.

    If you are looking specifically at boot time requirements then please refer to the bootloader application notes for OMAPL138

    Hope this helps answer your question. Let me know if you still have any questions.

    Regards,

    Rahul

  • Dear Rohit,

      Can you please send link for relevant document regards ECC on OMAPL13x/AM18x device.

    Regards

    Jithin

     

  • Hi Jithin,


    The documentation for using ECC support on EMIFA interface is part of the device TRM. Please refer to chapter 20 of the document provided below:

    In addition to this you can refer to the Bootloader user guide to look at boot specific requirements. If you are looking for software then utilities to write to NAND and the NAND driver can be found in Bootloader and Flash utilities

    Bootloader and FLash utilties:

    Thanks and Regards,

    Rahul