Hello all,
Im using DMA first time, I have custom board with C5501 interfaced to RAM inside FPGA . My FPGA configuration seems fine clock is running up, I have double checked pin assignment for FPGA synthesis. For some reason my DMA is not driving address, I monitored this activity using Signal Tap logic analyzer on FPGA.
I have configured data width of ram inside FPGA as 32bit.
Im using CSL for DMA programming, My DMA configuration is as follows
DMA_Config single_element_write =
{ /* DMA configuration structure*/
DMA_DMACSDP_RMK(DMA_DMACSDP_DSTBEN_NOBURST , DMA_DMACSDP_DSTPACK_OFF, DMA_DMACSDP_DST_DARAMPORT0 , DMA_DMACSDP_SRCBEN_NOBURST , DMA_DMACSDP_SRCPACK_OFF,
DMA_DMACSDP_SRC_EMIF , DMA_DMACSDP_DATATYPE_32BIT), /* DMACSDP */
DMA_DMACCR_RMK( DMA_DMACCR_DSTAMODE_CONST, DMA_DMACCR_SRCAMODE_CONST, DMA_DMACCR_ENDPROG_OFF, DMA_DMACCR_WP_DISABLE, DMA_DMACCR_REPEAT_OFF,
DMA_DMACCR_AUTOINIT_OFF, DMA_DMACCR_EN_STOP, DMA_DMACCR_PRIO_HI, DMA_DMACCR_FS_ELEMENT, DMA_DMACCR_SYNC_EXTINT3), /* DMACCR */
DMA_DMACICR_RMK(DMA_DMACICR_AERRIE_OFF, DMA_DMACICR_BLOCKIE_ON , DMA_DMACICR_LASTIE_OFF, DMA_DMACICR_FRAMEIE_OFF, DMA_DMACICR_FIRSTHALFIE_OFF, DMA_DMACICR_DROPIE_OFF,
DMA_DMACICR_TIMEOUTIE_OFF), /* DMACICR */
(DMA_AdrPtr) 0x0000u, /* DMACSSAL */0x40u, /* DMACSSAU */
(DMA_AdrPtr) 0x37A8, /* DMACDSAL */0x00u, /* DMACDSAU */
1, /* DMACEN */
1, /* DMACFN */
0, /* DMACFI */
0 /* DMACEI */
};
Where, I want source address to be 0X400000(trying to read first element from FPGA ram) and destination address as 0x0037A8(this is maps to DARAM on DSP).
My sync event does happens I can see SYNC bit it in Interrupt Status Register (DMACSR) of C5501. I am able to read from DSP DARAM and write to DSP DARAM but not from EMIF port
At the moment nothing is being read for EMIF. My EMIF config is as follows
EMIF_Config emif_config = { //View SPRU621F (EMIF Ref guide)
0x0020, /* gblctl1 */ //EK1HZ = 0, EK1EN enable
0x0000, /* gblctl2 */ //EK2EN disable
0x0040, /* ce1ctl1 */ //TA:00, read strb:000000(not implemented), Mtype:0100,
0x0080, /* ce1ctl2 */ //WRITEsetup:0, WRITE STROBE:2 clk cycle
0x0040, /* ce0ctl1 */ //TA:00, read strb:000000(not implemented), Mtype:0100,
0x0080, /* ce0ctl2 */ //unused
0x0040, /* ce2ctl1 */ //TA:00, read strb:000000(not implemented), Mtype:0100,
0x0080, /* ce2ctl2 */ //unused
0x0040, /* ce3ctl1 */ //TA:00, read strb:000000(not implemented), Mtype:0100,
0x0080, /* ce3ctl2 */ //unused
0x0000, /* sdctl1 */ //unused
0x0000, /* sdctl2 */ //unused
0xFFFF, /* sdrfr1 */ //unused
0x00FF, /* sdrfr2 */ //unused
0x07FF, /* sdext1 */
0x0FFF, /* sdext2 */
0x0021, /* ce1sec1 */ //SNCCLK = 0,REN signal,SYNCWL- 0 cycle write latency,SYNCRL - 1 cycle read latency,
0x0021, /* ce0sec1 */ //
0x0021, /* ce2sec1 */ //
0x0021, /* ce3sec1 */ //
0x0000 /* cescr */ //4Mbyte per each CE space (CE(0-3)),
};
Just to be on safe side I have configured all CEs with same configuration as the is only one physical ram connected to DSP's EMIF port.
Im bit confused about shifting the address to match the byte address required by DMA.
Can some one put some light what im doing wrong.
Thanks in advance