EMIFWAIT

The EMIFWAIT signal can be used to hold off the completion of an asynchronous memory access to an external device.  If the delay needed for a read or write cycle is consistent then the proper delay can be programmed into the async config register for the chip select that you are using.  If the external device has a ready/busy output signal designed to extend a memory cycle then it can be connected to one of the EMIFWAIT signals.  Each of the EMIFWAIT inputs can be assigned to separate chips selects to associate it with the proper device. The wait signals are assigned to a specific chip select using the Async Wait Cycle Config Register.  Note that an access can't be held off indefinitely.  The EMIF access will timeout if the maximum wait period is exceeded to avoid stalling the DSP.  In addition the EMIF will remain busy while the EMIFWAIT signal is active.  You can't initiate an access to a second EMIF device while waiting for the wait from the first EMIF device.