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On the DM816x, is it possible to output digital video 60 fields per second from 60 frames per second input?

I am using the DM8168 with SDK version 5.03.01.15.  The HD_VENC is configured to output 2 fields from every frame, causing every other frame to be dropped.  Is there a way to confgure the VOUT0 to output one field per frame and still be compliant with the vertical sync requirements of CEA-861-D?

  • Hi,

    HD_VENC can be configured for Interlaced video formats or progressive video formats. For Interlaced video format it will output one field every 16.66ms for 60fps while for progressive formats it will output one frame every 16.66ms. It will never output two fields in one time frame period. If I have misunderstood your question can you please post it in more detail.

    Regards,

    Hardik Shah

  • Hardik:

          That doesn't appear to be the behavior I am seeing, at least the way SDK has the compositor configured anyway.  I looks to me like the HD_VENC outputs 2 fields per frame when configured for interlaced output, causing the OMX display component to have to drop every other frame to avoid backing up the syslink queues. 

          How do configure the various compositor components to output 1 field per frame?

    Neil

  • Hello?  Any body there?

    I must not be stating my problem correctly.  I will try again: 

    I have 60 frames per second coming into the display driver and 60 fields coming out of VOUT port. The port produces 60 fields by dropping a frame and then plays the next as two interleaved fields. Rather than dropping every other frame, I would like to play odd fields from odd frames and even fields from even frames. How would I do that?

    Neil

  • Hi,

     

    You can do this in application by merging two fields of different frames and submitting it to the driver..

     

    Thanks,

    Brijesh Jadav

     

  • Thanks, Brijesh.

     The CIG paragraph (2.4.2.2 Interlacer) in SPRUGX8 (21 June 2011) indicates that the chip is designed to do exactly what we want. How do we do that?

     We considered the splitting a frame in the application approach before posting this inquiry. That would have to be done after the decoder and display components. We would have to maintain extra buffers, plus we would have to let the display driver and all its internals know that the frame is actually a field.

    The CIG path seems more natural to the HW and SW flow.

    Neil

  • Hi,

     

    Which display component you are using? As such this feature is supported by the driver, but i am not sure if it is exposed by the display component you are using.

     

    Thanks,

    Brijesh Jadav

     

  • Brijesh:

    I am using the following components from SDK 5.03.01.15: omx-ti81xx-src_05_02_00_30 and HDVPSS_01_00_01_33.  Within the display component, Rev 1.0 of the following files: omx_vfdc.c, omx_vfdc_drvif.c and omx_vfdc_utils.c

    Neil

  • Hi,

     

    Please contact your local TI FAEs about same since HDVPSS is under NDA and it cant be discussed here on Public forums.

     

    Thanks,

    Brijesh Jadav