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What cycles does it take between two continous reads in AM335x GPMC?

RY9983
Guru 10570 points

Hello.
I need to calculate GPMC optimal performance as synchronous burst read timing.
Could you let me know?

When I read access to GPMC continuously,
what cycles does it take between 1st burst read and 2nd burst read?

I think it takes just one GPMC_FCLK clock cycle in best case.
Is the idea correct?

I appreciate your advice.
Best regards,
RY

  • 0
    Guru 10570 points

    Hello.
    It is cleard. I found the description on TRM.
    Thank you for your checking.

       SPRUh73f.pdf
       AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual
       http://www.tij.co.jp/product/jp/am3352
         (P409) Table 7-10. Idle Cycle Insertion Configuration

       上記テーブルの上から2行目に記載されています。
       First Access Type              : R
       BUSTURNAROUND Timing Parameter : >0
       Second Access Type             : R
       Chip-Selece                    : Same
       Addr/Data Multiplexed          : Nonmuxed
       CYCLE2CYCLESAMECSEN Parameter  : x
       CYCLE2CYCLEDIFFCSEN Parameter  : 0

       No idle cycles are inserted if the two accesses are well pipelined.

    Best regards,
    RY