Hello,
I was searching the web and found some buzz about HPI and caching issues. Not sure, if that was well motivated and applies to my system.
In our design we boot DSP over HPI, and later use HPI to make communication between ARM serving as host and DSP. To do that I allocated a memory section (so its position is fixed and known) which I partitioned in incoming and outbound buffers. We use L2 as memory, no external memory available. When host sends message to DSP it writes to incoming buffer and then triggers DSPINT. ISR on DSP side reads data from incoming buffer and process. If DSP to send message to host, it writes to outbound buffer and triggers HINT, then host reads message.
According to block diagram in SPRU578C, HPI performs access to L2 through EDMA. Then, according to SPRU656A cache coherency in automatically maintained for "for accesses by the CPU and EDMA to L2 SRAM".
Does this mean that in my design I should not bother about caching, and hardware will do its job for me?
Thanks in advance.
