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proper power up sequence clocking on C6678

jschipp
Intellectual 350 points
Other Parts Discussed in Thread: TMS320C6678

I have a question on the clock enable in the power on sequence of TMS320C6678. According to the data manual of 6678, “Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state with one leg high and one leg low.”

Now I cannot do that. My clock(DDRCLK, CORECLK,SRIOCLK for DSP will keep to be high impedance  until 1.5V IO is on. Does this cause a problem for DSP booting? Please advise.

 Best Regards,

John

  • 0
    TI__Mastermind 42545 points

    John,

    Once CVDD is valid the differential receivers for the clock buffers will active.  Holding one leg high and one leg low is the ideal state in order to prevent false clocks.  If you're clock driver isn't active until the 1.5V is present this may not be possible.  As long as you hold PORz low until all power supplies are valid and until the clock is active and has switched the appropriate number of times, your DSP should boot correctly.