Hello,
It appears that the DM8168 Display Timing Generator does not produce proper interlaced video timing for 1920x1080i, output from DVO2 VOUT0. In reference to the CEA-861D Specification, Figure 3 Timing Parameters for 1920x1080i @ 59.94/60 on page 20, in Field 2, cannot adjust the rising edge of Vertical Sync pulse by two and one half lines with respect to the falling edge of the Data Enable pulse. The DM8168 Display Timing Generator half line adjustment does not work even though HF_LINE is set in register HD_VENC_cfg0 bit 28.
Here is a dump of HD_VENC Registers for the DTG configured for 1080i:
md 4810A000 38
4810A000 5401305A 003F0275 1EA500BB 1F9901C2 T.0Z .?.u .... ....
4810A010 1FD71E67 004001C2 00200200 1B6C0C77 ...g .@.. . .. .l.w
4810A020 1C0C0C30 1C0C0C30 84465898 2C248015 ...0 ...0 .FX. ,$..
4810A030 2C7880BD 00000231 00038338 2C780118 ,x.. ...1 ...8 ,x..
4810A040 00016000 0021C248 0500221C 05001233 ..`. .!.H ..". ...3
4810A050 00238234 2C780110 00016001 0021C248 .#.4 ,x.. ..`. .!.H
4810A060 0500121C 05004226 00000000 00000000 .... ..B& .... ....
4810A070 00000000 00000000 00000000 00000000 .... .... .... ....
4810A080 00000000 00000000 00000000 00000000 .... .... .... ....
4810A090 00000000 00000000 00000000 00000000 .... .... .... ....
4810A0A0 00000000 00000000 00000000 00000000 .... .... .... ....
4810A0B0 00000000 00000000 00000000 00000000 .... .... .... ....
4810A0C0 00000000 00000000 00000000 00000000 .... .... .... ....
4810A0D0 00000000 00000000 00000000 00000000 .... .... .... ....
Is it possible to tweak the DTG to make it comply with CEA-861 1920x1080i (Format 5) standard?
Best Regards,
Jeff
