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c6678 EDMA0 and EDMA1 with hyperlink

si cheng
Expert 2685 points

hello:

1. I use the EDMA0 and EDMA1 transfer data at the same time from DDR to MSM RAM, and then I test the transfer Bandwidth of EDMA0,  find that the Bandwidth is about 5GB/S,  if I do this only with EDMA0, the Bandwidth of EDMA0 is about 10GB/S. I want to know what happens when the EDMA0 and EDMA1 transfer data from DDR at the same time?

2. I want to know that if I transfer data from  DDR to the MSM RAM of remote device with EDMA0 by hyperlink, is the Bandwidth the same with transferring from DDR to local MSM RAM with EDMA0?

thanks!

  • 0
    TI__Intellectual 2415 points

    Cheng,

    1) In this scenario, the limitation is the DDR3 bandwidth (which is 10.6 GB/s @ 1333 MHz). When both EDMA0 and EDMA1 try to read the DDR3 memory at the same time, the DDR3 bandwidth is shared by both EDMA0 and EDMA1 masters. Whenever only EDMA0 is using the DDR3, we can achieve the complete 10 GB/s of DDR3 bandwidth.

    2) The max DDR3 to local MSMC throughput with EDMA0 is approx 10 GB/s. Where as the max chip to chip hyperlink bandwidth (4x lanes) is 40 gbps (5 GB/s). Hence, the max DDR3 to remote MSMC throughput is always less than 5 GB/s (from this 5 GB/s we need subtract the time it takes for the hyperlink master (on the remote DSP)  to write the incoming data into MSMC memory).

    I hope this helps.

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 300 points

    Hi, Sankar!

    According Hyperlink data mannual, the throughput of hyperlink should be 40gbps with 4 lanes when each of lane configured 10Gbps. 

    But when i test this throughput with edma cc1 from c6670 to c6678, the result is around 20Gbps instead of 40Gbps. the configuration is  as below,

    1) serdes reference clock: 250Mhz

    2) pll mpy is 10x and full speed is configured, so line rate per lane is 250*40 = 10Gbps.

    3) 4 lanes are actived.

    3) EDMA cc1, Acnt = 31KB, Bcnt = 100.

    Then i use edma move 3100KB data from c6670 to a 6678 buffer , which address is mapped into hyperlink space.

    The result is thoughput of hyperlink inter-dsp ddr-to-ddr is 20.8Gbps, while throughput of intra-dsp ddr-to-ddr edma cc1 is 39Gbps.

    I am confused by this result, i know in hyperlink module the 8b9b encoding and mac control header may reduce some throughput,  and it maybe

                                             40Gbps * 8/9 * 31/32 = 34.44Gbps                 (1 control packet every 32 packets.)

    So, i think my result of 20.8Gbps is not correct anyway.