Clock skew if using a clock distributor for two ethernet phys

Rodrigo Aznar Mendes

Other Parts Discussed in Thread: CDCLVC1106

Hi Folks,

We are going to implement two ethernet ports (RMII) with AM335X. Our intention is to use only one 50MHz oscillator as source to four points: the REF_CLK of the two MACs on AM335X and the CLKIN input of each phy. So we are assuming to use a clock distributor / clock fanout buffer as a way to have a good signal at each point.

Question is: Clock distributors have a skew between each output line. In this particular scenario, what would be an acceptable skew value between the clock that source the MAC and the clock that source its respective PHY?

Take as reference a clock distributor from TI, the CDCLVC1106 that have a maximum skew of 50 ps (output to output).

Thanks,

Rodrigo

over 12 years ago

0 Rodrigo Aznar Mendes over 12 years ago

Prodigy 215 points

Hello,

Does anyone from TI would have a feeling on the question raised?

Thanks a lot

Rodrigo

0 peaves over 12 years ago in reply to Rodrigo Aznar Mendes

TI__Guru 59235 points

Timing analysis should be performed for each RMII.

The timing analysis should incorporate all timing parameters of AM335x, RMII PHY, and PCB. For example, input setup/hold requirements, output delays, PCB propagation delays, rise/fall times, and clock skew.

So the answer to this question depends on the results of the timing analysis which depends on the RMII PHY selected and the PCB layout.

Regards,
Paul

0 Rodrigo Aznar Mendes over 12 years ago in reply to peaves

Prodigy 215 points

Hi Paul,

Thanks for remind us. If anyone have other empirical data using clock fanout buffers, please share with us.

Regards

Rodrigo

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Clock skew if using a clock distributor for two ethernet phys