Dear Sir,/Madam
We are designing our new product which is using C6678 DSP
And currently, we have two questions about 6678DSP:
1:
In the DDR3 Design Datasheet: SPRABI1A, about UDIMM Pin Mapping:
page 116 DDRCLKOUTP0/N0 <=> CK1/CK1#
at the same time, page 119 DDRCLKOUTP0/N0 <=> CK0/CK0#.
Is this correct? Or CK1/CK1# should be connected to DDRCLKOUTP1/N1, not CLKOUTP0/N0?
2:
Can 6678DSP support SODIMM?
Thank you
Regards,
Jin HAO