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Power Gating of CPU's

Siva Penke
Prodigy 50 points
Other Parts Discussed in Thread: 4460

Hi,

I am new to OMAP4 processors. I got hold of Public TRM for OMAP4's 4460 processor. I am doing power measurements as part of my project on Samsung Galaxy Nexus. I have some questions regarding this -

1] Does both the CPU's on 4460 processor are power gated separately? If yes, can you refer to the section in TRM that explains this? I didn't find any.

2] Is my understanding correct, that 4460 CPU's are single clock'ed? and to put the CPU in Retention mode, the clock is gated where as to put in OFF mode the CPU's are power gated?

3] The latency values to put the CPU is one of the C-states are hard-coded in the Linux_v3.0.8. For example, as per the time file in sysfs in /sys/devices/system/....cpuo/time for state3 it is defined as 1500us whcih is defined as the time taken from idle task to wfi and from wfi to task context. How are these values measured?

Thanks for your time and appreciate your response.

Best Regards

Siva Penke

  • 0
    TI__Intellectual 815 points

    Hello Siva,

    1.) From a hardware perspective, the 2 CPUs on the 4460 can have their power shut off separately, but depending on what software release and cpufreq governor you are using, the behavior will differ.  For example, in android kernel 2.6.35, the hotplug governor will online/offline the second CPU separately.  In android kernel 3.0, both CPUs are brought down at the same time.  Section 4.3.6.1 in the 4460 TRM shows the two CPUs as separate power domains.

    2.) I'm not sure what you mean by single clocked, but both CPUs run at the same frequency.  As for gating the clock and shutting down the power domain of the CPU, it depends on the C-state being entered.  Referring to the Android kernel code (arch/arm/mach-omap2/cpuidle44xx.c), the WFI and INA states gate the clocks.  However, the OFF state shuts down the power domain of the CPU in addition the having the clock gated.  This snippet is from cpuidle44xx.c:

    /* C1 - CPUx WFI + MPU ON + CORE ON */
    #define OMAP4_STATE_C1 0
    /* C2 through C4 are shared C-states, both CPUs must agree to enter */
    /* C2 - CPU0 INA + CPU1 INA + MPU INA + CORE INA */
    #define OMAP4_STATE_C2 1
    /* C3 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE CSWR */
    #define OMAP4_STATE_C3 2
    /* C4 - CPU0 OFF + CPU1 OFF + MPU OSWR + CORE OSWR */
    #define OMAP4_STATE_C4 3

    3.) The exit latency values for each C-state were measured through extensive testing.

    Regards,

    Alex

  • 0 in reply to Alex Trinh
    Prodigy 50 points

    Thanks Alex for the clear explanation.

    Best Regards

    Siva Penke

  • 0 in reply to Siva Penke
    Prodigy 50 points

    Hi Alex,

    From ARM Cortex A9 manual which is used in OMAP 4460 processor.. it is said that "Wait for Interrupt mode disables all the clocks of a Cortex-A9 processor, while keeping its logic powered up. This reduces the power drawn to the static leakage current." If WFI reduces the static leakage current, can I say that the static power consumption caused by the leakage currents is Zero in case of C4 state (CPU's OFF mode) ?

    Thanks for your time.

    Best Regards

    Siva Penke

    Reference: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0407e/CACGJGEE.html

  • 0 in reply to Siva Penke
    Prodigy 50 points

    Hi,

    I am working on Omap4460 processor on Samsung Galaxy Nexus using Linux kernel 3.0.8. 

    In file cpuidle44xx.c, the C4 state is defined as "C4 - CPU0 OFF + CPU1 OFF + MPU CSWR + CORE OSWR". Does CPUx OFF means a logical or physical offline of the CPU? (My understanding of logical OFF is that the CPU can't execute any more instructions but it is not hot plugged from the power source, instead it is removed from kernel's visibility.)

    Also, writing a zero to cpu1/online makes the CPU1 go offline (is this offline a logical or physical?). This is checked by looking at the tasks (user applications) migrating from CPU1 to CPU0. Also from /proc/interrupts it is clear that the CPU1 doesn't handle any more interrupts.

    However, when I do the same on CPU0, it doesn't allow me to put CPU0 to offline even when it is idle. Does this mean that CPU0 can't put in offline mode or is it because of the user's UART interrupt wakes-up CPU0  automatically?

    Thanks a ton in advance for clearing these doubts.

    Best Regards

    Siva Penke

  • 0 in reply to Siva Penke
    TI__Intellectual 2505 points

    Please start anotehr thread for these new questions.

    Thank you,

    Magdalena