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EMIF-A Sysclock fixed to 25MHz

Martin Kaul
Prodigy 110 points

Other Parts Discussed in Thread: OMAP-L138

Hi,

while configuration the EMIF-A settings of our OMAP-L138 EVA Board and monitoring the signals with a logic analyser I found out that it seems that the internal clock of the EMIF-A is fix set to 25MHz indepently of the SYSCLK3 settings.

(all files part of the attachted ZIP-File)

  • My SYSCLK3 setting is 100MHz - see attachted file PLL0-setting.bmp
  • In attachted file RSetup_0.TIF you can see the Setuptime between CS2 and OE is 40ns - the R_Setup was set to 0.
  • In attachted file RSetup_1.TIF you can see the Setuptime between CS2 and OE is 80ns - the R_Setup was set to 1
  • Increasing the setup time by 1 yields to a time difference of 40ns, i.e. the used clock is 25MHz and not 100MHz.

The OMAP caption is: XOMAPL138ZCE   $7-94A7K9W
The SYSCFG - REVID is 0x4E840102

Is there a other configuration register that yields to this behaviour?

Best regards
  Martin Kaul

OMAP-EMIFA.zip
  • 0
    Expert 1950 points

    Hello,

    From another point of view, the WE pulse preceding the read seems to be 10 ns long, involving a 100 MHz EMIFA clock.

    Can you display the associated CEnCFG register value in both cases ?

    The other setting involving EMIFA frequency is the EMA_CLKSRC bit in CFGCHIP3 register, which (if set) will produce an out-of-spec 133-MHz clock (ie 600 MHz PLLC0 divided by 4.5).

    Jakez