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EMIF16 Asynchronous Read

dp
Intellectual 990 points

Hi,

I want to interface FPGA and C6678 via EMIF16. And have some questions about asynchronous memory read timing:
1. What's the strobe signal ?
2. Is "setup/strobe/hold" basic demands? Who's demands, FPGA's or DSP's ?
3.what's the minimum required cycles of "setup/strobe/hold" ? I have look around the manual, but didn't find the clear description ?

4. What's the practical throughput ?

Thanks.
dp

  • 0
    TI__Guru* 84110 points

    dp,

    Please see section 2.5.2 Programmable EMIF16 Parameters for a description of the setup/strobe/hold timing parameters and the signals to which they relate.

    The timing waveforms a few pages later show you which signals change during the three timing periods.

    The minimum cycles are 3, when the setup/strobe/hold parameters are all set to 0.

    Practical throughput is very dependent on your requirements. The best throughput is achieved when you use the EDMA3 or Packet DMA to transfer a large burst of data to sequentially incrementing addresses. In that case you can achieve full speed of the number of cycles programmed into the setup/strobe/hold registers (+3, of course).

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 990 points

     Thanks RandyP for your reply.

     Regards,

    dp 

     

     

  • 0 in reply to dp
    TI__Guru* 84110 points

    dp,

    In some cases of use of the EMIF16, we have found that an unused internal feature can cause unintended delays between some EMIF16 accesses. This feature can be disabled by setting the msb of 0x20C00008 to 1. I recommend setting this in all cases for the C6678, and placing it near the top of your main() function.

    *(Uint32*)0x20C00008 |= 0x80000000;  // Disable unused internal EMIF feature

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 990 points

    Thanks RandyP。