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Hi,
I am using the OMAP L138 and am developing with CCS5 at sys/bios
i need in my project to tie edma with mcasp under sys/bios
first i use LLD it not compatible with sys/bios
then i decide to use CSL to configure edma & BSL to configure MCASP & AIC
i make a mini project to check mcasp with edma (sound echo)
now i face a problem no sound out and beeeep out
this code for set up edma (ping pong )
void setup_EDMA (void)
{
Uint16 i;
// Write EMCR, CCEERCLR, ECR registers to clear the EMR, CCERR, ER
// EMCR = 0xFFFFFFFF; CCERRCLR = 0xFFFFFFFF; ECR = 0xFFFFFFFF;
// EDMA event 0-- McASP0 Receiver
// EDMA event 1-- McASP1 Transmitter
// Clear Event Registers
CSL_FINST(edma3ccRegs->ECR, EDMA3CC_ECR_REG, MASK);
CSL_FINST(edma3ccRegs->SECR, EDMA3CC_SECR_REG, MASK);
/*CSL_FINST(edma3ccRegs->IECR, EDMA3CC_IPR_REG, MASK);
CSL_FINST(edma3ccRegs->ICR, EDMA3CC_IPR_REG, MASK);*/
edma3ccRegs->ECR = 0xffffffff; // clear events 0 -> 31
edma3ccRegs->SECR = 0xffffffff; // clear secondary events 0 -> 31
edma3ccRegs->IECR = 0xffffffff; // disable all interrupts
edma3ccRegs->ICR = 0xffffffff; // clear all pending interrupts
// Enable Channel 2 - 3 to DSP (Region 1 )
// CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E2, ENABLE);
// CSL_FINST(edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE, EDMA3CC_DRAE_E3, ENABLE);
edma3ccRegs->DRA[CSL_EDMA3_REGION_1].DRAE =
CSL_FMKT(EDMA3CC_DRAE_E0, ENABLE) |
CSL_FMKT(EDMA3CC_DRAE_E1, ENABLE);
// Assign Channel 2 - 3 to Queue 0
edma3ccRegs->DMAQNUM[1] =
CSL_FMKT(EDMA3CC_DMAQNUM_E0, Q0) |
CSL_FMKT(EDMA3CC_DMAQNUM_E1, Q0);
// Initialize PaRAM Transfer Context for Events 2 - 3
init_PaRAM_McASP_Rcv_event0();
init_PaRAM_McASP_Tx_event1();
// Enable channel 0 and 1
CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E0, SET);
CSL_FINST(edma3ccRegs->EESR, EDMA3CC_EESR_E1, SET);
// Enable interrupt 0 and 1
CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I0, SET);
//CSL_FINST(edma3ccRegs->IESR, EDMA3CC_IESR_I3, SET);
//CSL_FINST(IER, CHIP_IER_IE08, ENABLE ); // Enable Interrupt 8
// Init buffers
for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER; i++)
{
pingRcvBuffer_L[i] = 0; pingRcvBuffer_R[i] = 0;
pongRcvBuffer_L[i] = 0; pongRcvBuffer_R[i] = 0;
pingXmtBuffer_L[i] = 0; pingXmtBuffer_R[i] = 0;
pongXmtBuffer_L[i] = 0; pongXmtBuffer_R[i] = 0;
}
//for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER*8; i++) TestData[i] = i;
// Manually Enable Event 2
//CSL_FINST(edma3ccRegs->ESR, EDMA3CC_ESR_E2, SET);
}/* setup_EDMA */
/*---------------------------------------------------------------------------*/
void init_PaRAM_McASP_Rcv_event0 (void)
{
Uint32 ping_offset_Rcv = (Uint32)pingRcvBuffer_R - (Uint32)pingRcvBuffer_L,
pong_offset_Rcv = (Uint32)pongRcvBuffer_R - (Uint32)pongRcvBuffer_L;
Int16 ping_c_idx_Rcv = -ping_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE,
pong_c_idx_Rcv = -pong_offset_Rcv + NUM_OF_BYTES_PER_SAMPLE;
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT0].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT0].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT0);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT0].SRC = (Uint32) &(mcaspRegs-> RBUF12); //&pingSrcBuffer; (Uint32)&mcaspRegs->RBUF12;
edma3ccRegs->PARAMSET[EDMA_EVENT0].DST = (Uint32) &pingRcvBuffer_L[0]; //&RcvBuffers_1[0]; // (Uint32)&u32_Rcv_Buffer[0u];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT0].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_EVENT0].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT0].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT0].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT0].LINK_BCNTRLD =
//CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)0xFFFF) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET64] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); // 0080h CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
//************** Parameter Set 34 *******************//
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT0);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC = (Uint32) &(mcaspRegs-> RBUF12); //&pingSrcBuffer; (Uint32)&mcaspRegs->RBUF12;
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].DST = (Uint32) &pongRcvBuffer_L[0]; //&RcvBuffers_2[0]; //&RcvBuffers[2*NUM_OF_SAMPLES_PER_BUFFER]; // (Uint32)&u32_Rcv_Buffer[0u];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, pong_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, pong_c_idx_Rcv); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET64] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER); // 0080h CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
//************** Parameter Set 36 *******************//
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT0);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].SRC = (Uint32) &(mcaspRegs-> RBUF12); //&pingSrcBuffer; (Uint32)&mcaspRegs->RBUF12;
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].DST = (Uint32) &pingRcvBuffer_L[0]; //&RcvBuffers_1[0]; // (Uint32)&u32_Rcv_Buffer[0u];
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, ping_offset_Rcv); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, 0) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, ping_c_idx_Rcv); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET36].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET64] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER); // 0080h CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
}
/*---------------------------------------------------------------------------*/
void init_PaRAM_McASP_Tx_event1 (void)
{
Uint32 ping_offset_Xmt = (Uint32)pingXmtBuffer_R - (Uint32)pingXmtBuffer_L,
pong_offset_Xmt = (Uint32)pongXmtBuffer_R - (Uint32)pongXmtBuffer_L;
Int16 ping_c_idx_Xmt = -ping_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE,
pong_c_idx_Xmt = -pong_offset_Xmt + NUM_OF_BYTES_PER_SAMPLE;
// this was for event11
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_EVENT1].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_EVENT1].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT1);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_EVENT1].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_EVENT1].DST = (Uint32) &(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_EVENT1].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_EVENT1].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_EVENT1].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_EVENT1].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_EVENT1].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET65] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //*NUM_OF_SAMPLES_PER_BUFFER); // CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
//************** Link to parameter set 35 *******************//
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT1);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC = (Uint32) pongXmtBuffer_L; //&XmtBuffers_2[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].DST = (Uint32) &(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, pong_offset_Xmt) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, pong_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET65] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); // CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
//************** Link to parameter set 37 *******************//
// Reset EDMA PaRAM OPT Register
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].OPT = CSL_EDMA3CC_OPT_RESETVAL;
// Config PaRAM OPT (Enable TC Interrupt & ITC Chaining; Set TCC)
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].OPT =
CSL_FMKT(EDMA3CC_OPT_ITCCHEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_TCINTEN, DISABLE) |
CSL_FMKT(EDMA3CC_OPT_SYNCDIM, ASYNC) |
CSL_FMK(EDMA3CC_OPT_TCC, EDMA_EVENT1);
// Initialize EDMA Event Src and Dst Addresses
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].SRC = (Uint32) pingXmtBuffer_L; //&XmtBuffers_1[0]; // (Uint32)&u32_Xmt_Buffer[0u];
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].DST = (Uint32) &(mcaspRegs->XBUF11); // (Uint32)&pongDstBuffer; //
// Set EDMA Event PaRAM A,B,C CNT
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].A_B_CNT =
CSL_FMK(EDMA3CC_A_B_CNT_ACNT, NUM_OF_BYTES_PER_SAMPLE) | //0004h
CSL_FMK(EDMA3CC_A_B_CNT_BCNT, 2); //2*NUM_OF_SAMPLES_PER_BUFFER); //0080h
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].CCNT = NUM_OF_SAMPLES_PER_BUFFER; // NUM_OF_BUFFER; // //0001h
// Set EDMA Event PaRAM SRC/DST BIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].SRC_DST_BIDX =
CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, ping_offset_Xmt) | // //0000h// CSL_FMK(EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0u) |
CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, 0); //NUM_OF_BYTES_PER_SAMPLE); // //0001h CSL_FMK(EDMA3CC_SRC_DST_BIDX_DSTBIDX, NUM_OF_BYTES_PER_SAMPLE);
// Set EDMA Event PaRAM SRC/DST CIDX
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].SRC_DST_CIDX =
CSL_FMK(EDMA3CC_SRC_DST_CIDX_SRCCIDX, ping_c_idx_Xmt) | // 0000h
CSL_FMK(EDMA3CC_SRC_DST_CIDX_DSTCIDX, 0); //0); // 0000h
// Set EDMA Event PaRAM LINK and BCNTRLD
edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET37].LINK_BCNTRLD =
CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35] & 0xFFFFu) | // CSL_FMK(EDMA3CC_LINK_BCNTRLD_LINK, (Uint32)&edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET65] & 0xFFFFu) |
CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, 2); // CSL_FMK(EDMA3CC_LINK_BCNTRLD_BCNTRLD, NUM_OF_SAMPLES_PER_BUFFER);
}
EDMA isr
void EDMA_INT_isr(void)
{
Int32 *data_in_L;
Int32 *data_in_R;
Int32 *audio_out;
interrupt_counter += 1;
run = 0;
while(edma3ccRegs->IPR != 0)
{
// Clear Pending Interrupt
edma3ccRegs->ICR |= 0x0001; //edma3ccRegs->ICR = 0x00000004;
}
if (PingPongFlag_Rcv){
PingPongFlag_Rcv = 0;
data_in_L = pingRcvBuffer_L;
data_in_R = pingRcvBuffer_R;
audio_out = pingXmtBuffer_L;
//edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].DST = (Uint32) &RcvBuffers_1[0];
//edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].DST = (Uint32) &XmtBuffers_1[0];
while(!CHKBIT(MCASP->SRCTL11, XRDY));
for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER; i++){
pingXmtBuffer_L[i] = pingRcvBuffer_L[i];
pingXmtBuffer_R[i] = pingRcvBuffer_R[i];
}
// memcpy (pingXmtBuffer_L, pingRcvBuffer_L, NUM_OF_SAMPLES_PER_BUFFER * sizeof(Int32)); //copy RCV to XMT
// memcpy (pingXmtBuffer_R, pingRcvBuffer_R, NUM_OF_SAMPLES_PER_BUFFER * sizeof(Int32)); //copy RCV to XMT
} else {
PingPongFlag_Rcv = 1;
//edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET34].DST = (Uint32) &RcvBuffers_2[0];
//edma3ccRegs->PARAMSET[EDMA_PARAMETER_SET35].DST = (Uint32) &XmtBuffers_2[0];
data_in_L = pongRcvBuffer_L;
data_in_R = pongRcvBuffer_R;
audio_out = pongXmtBuffer_L;
while(!CHKBIT(MCASP->SRCTL11, XRDY));
{}
for(i = 0; i < NUM_OF_SAMPLES_PER_BUFFER; i++){
pongXmtBuffer_L[i] = pongRcvBuffer_L[i];
pongXmtBuffer_R[i] = pongRcvBuffer_R[i];
}
// memcpy (pongXmtBuffer_L, pongRcvBuffer_L, NUM_OF_SAMPLES_PER_BUFFER * sizeof(Int32)); //copy RCV to XMT
// memcpy (pongXmtBuffer_R, pongRcvBuffer_R, NUM_OF_SAMPLES_PER_BUFFER * sizeof(Int32)); //copy RCV to XMT
}
}
