C6678 Jtag problem

Bonzai,

Maybe you can start by providing use with the following.

1.) What version of CCS are you using?  And how do you have it configured?

2.) What error messages are you getting when you attempt to connect?

3.) A capture of the emulation portion of the board soe we can evaluate the connection.

Best Regards,

Chad

1.> I'm using CCSV5.  I have 4 jtag headers, one for each DSP.  I have bootmode[2:0] pull-up high with 4.99k and the rest of bootmode connect to FPGA for dynamic config.

2.> the error message I have as following:

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]

-----[Print the board config pathname(s)]------------------------------------

C:\DOCUME~1\pyeung\LOCALS~1\APPLIC~1\.TI\
    213602635\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 560-class product.
This utility will load the program 'bh560ubp.out'.
The library build date was 'Apr  2 2012'.
The library build time was '21:47:30'.
The library package version is '5.0.681.0'.
The library component version is '35.34.39.0'.
The controller does use a programmable FPGA.
The old VHDL code has a version number of '0' (0x00000000).
The new VHDL code has a version number of '386336272' (0x17070610).

An error occurred while hard opening the controller.

-----[An error has occurred and this utility has aborted]--------------------

This error is generated by TI's USCIF driver or utilities.

The value is '-183' (0xffffff49).
The title is 'SC_ERR_CTL_CBL_BREAK_FAR'.

The explanation is:
The controller has detected a cable break far-from itself.
The user must connect the cable/pod to the target.

[End]

 3.> the jtag schematic as follwoing:

Are you using an adaptor between the JTAG header on the board and the pod?  These can sometimes be damaged and result in a cable break error message.  Also, have you verified the device is up and out of reset?

Do you have another JTAG pod you can try to use?

Best Regards,

Chad

Bonzai,

Can you confirm that you have measured CVDD, CVDD1, DVDD18 and DVDD15 and that they are at the proper voltage levels.  You stated that you have sequenced the PORz and the RESETFULLz as shown in the data manual.  Can you also confirm that the CORECLK is toggling when PORz and RESETFULLz are released?

Bill

there is no adapter, the pod is connect directly to jtag header on board.  the same pod is used with eval board and working fine.

I beleive the dsp device is up and running since we provide the 100MHz clock and we measure the sysclkout is 16.7MHz.  we scope the resetstatn is high.

thanks,

Thien

I have

CVDD = 0.989V

CVDD1 = 1.01V

DVDD18 = 1.78V

DVDD15 = 1.5V

the coreclk is toggle at 100MHz and sysclkout toggle at 16.7mhz

That sysclkout would indicate the device's PLL is still in Bypass (i.e. core's trying to run at 100MHz.) Not sure that the emulation is going to connect when it's running that slow. What bootmode are you using?  What are you bootmode pins tied to?  As Bill requested can you probe the PORz and RESETFULLz pins?

Best Regards,
Chad

In addition could you provide the portion of the schematic on page 2 that shows the connection to the JTAG connector?  Generally the only requirements for connection with JTAG are the proper voltages, the clock input and the proper sequencing of the reset signals so we are trying to look for any possible problems.

when I scope the PORz, resetfull, and resetstat, the PORz go high first and then Rresestfull and finally resetstat.  I'll post the scope signals if needed.

the schematic page 2 and bootmode are below

I'm glad to hear that it's working.  If this solves your issue could you hit that verify answer button so we can close the entry?

Thanks, Bill

one more thing, the pin 4 of jtag header need to connect to ground.  to summary the fix is:

for 20-pin jtag header:

1.> connect pin 9 to pin 11 via 22 ohms resistor

2.> connect pin 4 to pin 8