2.30 BSP watchdog timer with DVFS

I am using an OMAP3503 with the 2.30 BSP. I have the internal watchdog timer enabled for software protection. If the watchdog times out the processor does a warm boot. I have verifies this works and does indeed reboots correctly but only if I do not have the DVFS catalog item enabled. I can tell from the reset status register the cause was a watchdog reset. If the DVFS is enabled with CPU load policy and the watchdog fires after power up but before the first switch to a lower OPP it also resets OK. But if I wait until it switches to a lower or different OPP then the watchdog fires it seems to stall …I believe the stall is in the on chip firmware loader or the XLDR power up as I do not even get the first XLDR debug message on the debug console. It is locked up and never comes up. I can only power cycle to recover. I really do not have any means to debug this sort of issue. Can anyone help? Could there be some registers that are reset upon power on but not watchdog reset? Could it be some clocking or power domain issue? Could it have something to do with the PMIC (TPS65930)?