Reading the Clocking design guide for the Keystone family, table 3 indicates that the PCIe clock (PCLK) can be internally or externally supplied. Reading over the PCI guide, it implies that the signal can only be external.
I am trying finalize a clocking strategy for a 6657 and I am trying to keep the number of clocks required down to 3 inputs.
Currently I am planning on using:
1. Core - 100MHz
2. DDR2 - 50MHz or 66MHz
3. SRIO - 250MHz (for SGMII)
4. MCM - Not used, will be terminated
5. PCIe - 100MHz
If the PCIe clock can be coupled to the core clock internally, this would allow me to go to a 3 clock system into the CPU.
Paul
