Hello,
We are running a system using the C6748 module on the TMDSEVML138 board and having problems with flow control on the UARTs. We have followed the PSP polling loopback code example for the UART, changed the configuration for our system and enabled FIFO mode but RX data is being lost when the code isn't constantly polling the RBR port. If the code sits in a loop and constantly polls the RBR port we don't have a problem, but when the code does another task and then comes back to the RX port then data is lost. Flow control pin RTS is being driven and data is being throttled at some stage (RTS toggling for C6748) when sending a long file from Teraterm, however bits are being lost and the UART is reporting framing errors. We've tried both UART2 and UART0 with same results. It looks like we've setup everything correctly, both C6748 UART and PC serial ports are hardware flowed enabled and we see RTS in both directions being asserted during a transaction but data is still being lost?
We've modified the TMDSEVML138 board so CTS buffer going to C6748 UART2 (DEEPSLEEP_nEN) is always enabled.
Code attached. Function test_rx is called during IDLE.
CCS version 5.2.0.00069
SYSBIOS version 6_33_04_39
PSP version 01_30_01
GEL v1.1, 1016314A Release (files dates 7/2/2010)
Thanks.
Mark
//-----------------------------------------------------------------------------
// Title: uart.c
// File:
// Rev: 0.1
// Date: 29-06-2012
// Author: MB
//-----------------------------------------------------------------------------
#include "main.h"
#include "\ti\pspiom\cslr\csl_types.h"
#include "\ti\pspiom\cslr\soc_OMAPL138.h"
#include "\ti\pspiom\cslr\cslr_uart.h"
#include "\ti\pspiom\cslr\cslr_psc_OMAPL138.h"
#include <stdio.h>
#include "\ti\pspiom\cslr\cslr_syscfg0_OMAPL138.h"
CSL_UartRegsOvly uartRegs = (CSL_UartRegsOvly)CSL_UART_0_REGS;
void init_uart(void)
{
//line control register
uartRegs->LCR = CSL_FMKT(UART_LCR_WLS,8BITS) //word length 8bits
| CSL_FMKT(UART_LCR_SP,DISABLE)
| CSL_FMKT(UART_LCR_BC,DISABLE)
| CSL_FMKT(UART_LCR_STB,1BIT)
| CSL_FMKT(UART_LCR_PEN,DISABLE);
//modem control register
uartRegs->MCR = CSL_FMKT(UART_MCR_AFE,ENABLE) //RTS control
| CSL_FMKT(UART_MCR_LOOP,DISABLE) //loopback disable
| CSL_FMKT(UART_MCR_RTS,ENABLE); //auto flow disable
uartRegs->FCR = CSL_FMKT(UART_FCR_FIFOEN, ENABLE); // Enable RX Fifo
uartRegs->FCR = CSL_FMKT(UART_FCR_FIFOEN, ENABLE) // Enable RX Fifo
| CSL_FMKT(UART_FCR_RXFIFTL, CHAR1) // RX fifo 1 chars
| CSL_FMKT(UART_FCR_DMAMODE1,DISABLE);
uartRegs->IER = CSL_FMKT(UART_IER_ETBEI, DISABLE) // Disable TX Interupt
| CSL_FMKT(UART_IER_ERBI, DISABLE) // Disable ERBI Interupt
| CSL_FMKT(UART_IER_ELSI, DISABLE) // Disable ELSI Interupt
| CSL_FMKT(UART_IER_EDSSI, DISABLE); // Disable EDSSI Interupt
//divisor latch
// 9600 baud: 150MHz reference, 16x oversampling
CSL_FINS(uartRegs->DLL,UART_DLL_DLL,0xd1);
CSL_FINS(uartRegs->DLH,UART_DLH_DLH,0x3);
//enable transmitter and receiver
CSL_FINST(uartRegs->PWREMU_MGMT,UART_PWREMU_MGMT_UTRST,ENABLE);
CSL_FINST(uartRegs->PWREMU_MGMT,UART_PWREMU_MGMT_URRST,ENABLE);
}
void device_init(void)
{
CSL_PscRegsOvly psc0Regs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;
// deassert UART local PSC reset and set NEXT state to ENABLE
psc0Regs->MDCTL[CSL_PSC_UART0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE )
| CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );
// move UART PSC to Next state
psc0Regs->PTCMD = CSL_FMKT( PSC_PTCMD_GO0, SET );
// wait for transition
while ( CSL_FEXT( psc0Regs->MDSTAT[CSL_PSC_UART0], PSC_MDSTAT_STATE )
!= CSL_PSC_MDSTAT_STATE_ENABLE );
}
void test_rx(void)
{
char rec_val;
if (CSL_FEXT(uartRegs->LSR,UART_LSR_DR)!= 1)
{
return;
}
else
{
rec_val = CSL_FEXT(uartRegs->RBR,UART_RBR_DATA);
// Send to TX port
while(CSL_FEXT(uartRegs->LSR,UART_LSR_THRE)!= 1);
CSL_FINS(uartRegs->THR,UART_THR_DATA,rec_val);
}
}
//-----------------------------------------------------------------------------
// Title: main.c
// File:
// Rev: 0.1
// Date: 29-06-2012
// Author: MB
//-----------------------------------------------------------------------------
#include "main.h"
#include "uart0_only.h"
#include "\ti\pspiom\cslr\csl_types.h"
#include "\ti\pspiom\cslr\soc_OMAPL138.h"
#include "\ti\pspiom\cslr\cslr_uart.h"
#include "\ti\pspiom\cslr\cslr_psc_OMAPL138.h"
#include <stdio.h>
#include "\ti\pspiom\cslr\cslr_syscfg0_OMAPL138.h"
//--------------------------------------
// main()
//--------------------------------------
void main(void){
CSL_SyscfgRegsOvly sysRegs = (CSL_SyscfgRegsOvly)(CSL_SYSCFG_0_REGS);
/* Key to be written to enable the pin mux registers to be written
sysRegs->KICK0R = 0x83e70b13;
sysRegs->KICK1R = 0x95A4F1E0;
sysRegs->PINMUX0 = PINMUX0_VALUE;
sysRegs->PINMUX1 = PINMUX1_VALUE;
sysRegs->PINMUX2 = PINMUX2_VALUE;
sysRegs->PINMUX3 = PINMUX3_VALUE;
sysRegs->PINMUX4 = PINMUX4_VALUE;
sysRegs->PINMUX5 = PINMUX5_VALUE;
sysRegs->PINMUX6 = PINMUX6_VALUE;
sysRegs->PINMUX7 = PINMUX7_VALUE;
sysRegs->PINMUX8 = PINMUX8_VALUE;
sysRegs->PINMUX9 = PINMUX9_VALUE;
sysRegs->PINMUX10 = PINMUX10_VALUE;
sysRegs->PINMUX11 = PINMUX11_VALUE;
sysRegs->PINMUX12 = PINMUX12_VALUE;
sysRegs->PINMUX13 = PINMUX13_VALUE;
sysRegs->PINMUX14 = PINMUX14_VALUE;
sysRegs->PINMUX15 = PINMUX15_VALUE;
sysRegs->PINMUX16 = PINMUX16_VALUE;
sysRegs->PINMUX17 = PINMUX17_VALUE;
sysRegs->PINMUX18 = PINMUX18_VALUE;
sysRegs->PINMUX19 = PINMUX19_VALUE;
// lock the pinmux registers
sysRegs->KICK0R = 0x00000000;
sysRegs->KICK1R = 0x00000000;
//enable uart in the power and sleep controller
device_init();
//setup uart registers and start uart running
init_uart();
BIOS_start();
}
//----------------------------------------------------------------------------
uart0_only.h
//----------------------------------------------------------------------------
/*
MUX1 Pins:
MUX2 Pins:
UART0_RXD UART0_TXD UART0_CTS UART0_RTS
MUX3 Pins:
MUX4 Pins:
MUX5 Pins:
*/
#define PINMUX0_VALUE 0x00000000
#define PINMUX1_VALUE 0x00000000
#define PINMUX2_VALUE 0x00000000
#define PINMUX3_VALUE 0x22220000
#define PINMUX4_VALUE 0x00000000
#define PINMUX5_VALUE 0x00000000
#define PINMUX6_VALUE 0x00000000
#define PINMUX7_VALUE 0x00000000
#define PINMUX8_VALUE 0x00000000
#define PINMUX9_VALUE 0x00000000
#define PINMUX10_VALUE 0x00000000
#define PINMUX11_VALUE 0x00000000
#define PINMUX12_VALUE 0x00000000
#define PINMUX13_VALUE 0x00000000
#define PINMUX14_VALUE 0x00000000
#define PINMUX15_VALUE 0x00000000
#define PINMUX16_VALUE 0x00000000
#define PINMUX17_VALUE 0x00000000
#define PINMUX18_VALUE 0x00000000
#define PINMUX19_VALUE 0x00000000
