We have intermittent problems with the connection from SGMII to PHY. We use the Marvell 88E1111 Phy.
Sometimes, everything is fine and the LINK (bit 0) in SGMII STATUS register will be 1. In this case we have a perfectly working ethernet connection.
However, in about 1 out of 5 power-up cycles the SGMII STATUTS register LINK bit remains 0 after initialization. Resetting the device does not change the situation, only a new power cycle brings the device in a state where the LINK can be created.
We have tried to use loop-backs to narrow down the problem.
If we enable loop-back in the SGMII we get LINK UP always.
If we enable loop-back in the SERDES Tx we get LINK UP only if we get LINK-UP with PHY as well.
Here is our initializing sequence (serdes pll input clock is 250 MHz):
const int macPortNum = 1;
// set SERDES
CSL_BootCfgSetSGMIIConfigPLL (0x00000051);
CSL_BootCfgSetSGMIIRxConfig (macPortNum, 0x00704621);
CSL_BootCfgSetSGMIITxConfig (macPortNum, 0x000108A1);
do {
CSL_SGMII_getStatus(macPortNum, &sgmii_status);
} while (sgmii_status.bIsLocked != 1);
CSL_SGMII_doSoftReset (macPortNum);
while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);
// set SGMII
CSL_SGMII_startRxTxSoftReset (macPortNum);
CSL_SGMII_disableMasterMode (macPortNum);
CSL_SGMII_enableAutoNegotiation (macPortNum);
CSL_SGMII_endRxTxSoftReset (macPortNum);
sgmiiCfg.linkSpeed = CSL_SGMII_1000_MBPS;
sgmiiCfg.duplexMode = CSL_SGMII_FULL_DUPLEX;
CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);
do {
CSL_SGMII_getStatus(macPortNum, &sgmiiStatus);
} while (sgmiiStatus.bIsLinkUp != 1);
We have already tried various different settings but to no avail.
During POR we deassert RESET about 5 ms after clocks and power supply are stable and after 5 more ms we deassert POR.
Has somebody experienced such a situation ? And did you solve this ?
What can we try (hardware and/or software) to diagnose or solve this ?
Thank you very much in advance.
