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DPLLs in bypass mode during suspend state

Hi,

We have a custom DM37x based board. In this custom board we have implemented suspend state for the BSP to achieve the lowest possible power state. All the peripherals are configured to operate in Auto IDLE mode and SDRAM controller is configured to enter Self Refresh mode.

In addition we want to implement the following before entering the suspend state,

- Put CORE clock in the bypass mode (system clock)

- Put ARM and DSP in bypass mode (system clock)

- Put Peripheral 1 and Peripheral 2 clock in bypass mode (system clock)

 Few queries in this regard,

- Is this Technically feasible and has anyone tried this option?

- Will we see an impact on the SDRAM Controller & SDRAM device as we are putting the Core clocks in bypass mode?

Regards,

~Ajit