We're bringing up our own boards with C5515 using a design that is broadly similar to the TMDXEVM5515 .
One of the reasons for selecting the DSP was that we should be able to use the on-board LDOs for internal supplies, just providing 1V8. We discussed this approach with our local TI application support team (who have been very helpful) as well and no problems came up.
So we design our boards to provide 1V8 only. All the 1V3 rails are powered from the DSP_LDOO (we're planning to run at 120MHz so this would be used at 1V3).
Nothing comes up at all.
We're clearly not the first people to try to do this and hit this problem. It turns out that according to http://e2e.ti.com/support/dsp/tms320c5000_power-efficient_dsps/f/109/p/49648/176471.aspx you have to provide 1V3 to CVDDRTC *before* the DSP_LDO starts to function. If we'd known this we'd have fitted the C5505 instead, the only difference between them being the LDOs...
When we cut the track and patch 1V3 to CVDDRTC the DSP and rails come up as expected. We now have another 14 high-density PCBs that need an expensive hand modification, and have to make a design change that adds cost and space.
The post linked to above was from May 2010 and clearly TI application support are aware of this problem. The C5515 data sheet was updated in Jan 2012. There is *no* reference in the data sheet that says that CVDDRTC cannot be powered from DSP_LDOO or one of the other LDOs, although there are several places where this could be made clear. It is noted that CVDDRTC must be externally powered if the DSP_LDO is powered down in RTC sleep mode, but that's not something we plan to use. We only found the issue the hard way.
Hopefully this post will help others designing with this and similar CPUs to understand the requirement to provide multiple external PSU rails.
Quite frankly, the C5515 data sheet should be clearer about the need to provide external 1V3 to CVDDRTC, or it should be listed in the errata.
Kind regards,
Antony
