DM365 PLL settings

Jan,

Basically the issue is, PLL1 is not getting locked after this. But can you try putting a delay and try dumping the registers? I'm not sure about it, but is there a stabilization period required for this? I couldn't find much explanation regarding the PLL locking. I'm just guessing. 

Hi,

there is some locking period and the datasheet describes that the polling of status bits should be used. I have tried both, increasing the period and the polling but unfortunately nothing helped...

regards
Jan 

Hello Renjith,

I do have a question along the same line as Jan:

It's about CLKOUT2 on the TM320DMS365.

There is an input clock of 24MHz (at MXI/O) on the SoC.

I'd like to use CLKOUT2 to drive a device that needs a 32kHz clock, but I can't quite figure out if this is possible.

Does TI have a PLL divider tool to help? Or, do you know offhand if this will work?

I've combed SPRUFG5A but cannot figure out if I'm running my ARM core at full speed  (300MHz) if I can divide the Main PLL output clock down to 32KHz using PLLCL1SYSCLK9 and PLLDIV9.

Please let me know if you can help.

Cheers
Seb 

Seb,

I don't think you'll get to use 32KHz from CLKOUT2. Its better you go for an external PLL or crystal to get exact 32.768KHz.

Jan,

Best sources of information on clocking topic is the Data Sheet (SPRS457E, sec 3.3) and ARM Subsystem User's Guide (SPRUFG5A, chapter 5).

Regards.

Hi Renjith,

I thought this was for an RTC but it is not. A 32KHz pluse is needed to drive a WiFi module in sleep mode. It this still a no go?

Thanks

Seb

Seb,

Generally in Wi-Fi modules I've seen external crystals being used. Also it will not be accurate 32,768Hz even if you use generated clock. Also CLKOUT2 can be used for general purpose applications, like providing master clock for camera etc..

Jan,

  Please try to change your initializing orders of 2 PLLs when you want to get back from LP mode, sometime one PLL has to be initialized before or after the others, especially PLLs have some kinds of daise chain connection. 

Thanks!

 Phil

Hi Jan,

On page 148 of SPRUFG5A (Section 9.12.19 Peripheral Clock Control) the description for the ARMCLKS field states that:

When changing the source clock (either 0 to 1 or 1 to 0), ARM926 clock frequency must be Greater-than-or equal to CFG/DMA bus clock frequency (PLLC1SYSCLK4).

This doesn't quite match your test results, but at least it documents a requirement regarding the clocks.

best regards,

Soren

Hi Jan

Did you ever manage to get deepsleep working on the dm365.

I read through your code and I found that you treat "pll1_reg_base" as the cpu pll, however looking at "PERI_CLK_CTL: 0x243f04fc", bit 29 is set and from page 148 of SPRUFG5A, if this bit is set then the ARM926 clock source is PLLC2SYSCLK2.

I am also trying (for quite some time now) to get deep sleep working however, I am unable to wake up from deep sleep. The steps I followed are:

• Put cpu pll into bypass (clear pllensrc and pllen in pllctl register)
• Power down cpu pll (set pllpwrdwn in pllctl register)
• Set deepsleep wakeup delay to 128
• In SRAM:
  • Put ddr in self refresh (clear srpd and set lpmoden of sdrcr register)
  • Stop MCLK (set mclkstopen of sdrcr)
  • Disable DDR2 LPSC (Module 13 of PSC modules (table 39 of SPRUFG5A))
  • Disable clock to DDR PHY (clear plldiven of plldiv7 register)
  • Go into deep sleep (set deep sleep enable bit)
  • Poll sleep complete bit of deep sleep register (while in this loop the  a micro controller causes gpio0 to transition from high to low)
  • I am having an issue at this point as I am unable to wake up from sleep. I am using the micro controller to transition the gpio0 from low to high, which according to SPRUFG5A should wake it up from deep sleep.
  • If woken up, then remove deep sleep enable (clear deep sleep enable)
  • Enable clock to DDR PHY
  • Enable DDR LPSC
  • Start MCLK
  • Take ddr out of self refresh
• Power up cpu pll (clear pllpwrdwn in pllctl)
• Put cpu pll in bypass mode
• Reset cpu pll
• Do pllsecctl sequence 
• Poll the lock bits of pllc2_config register 
• Continue as normal...

If I remove the step to poll the deep sleep complete bit in the deep sleep register, the arm does not receive the transition of gpio0 from high to low and hence does not go into deep sleep. In this case, the program continues as normal and restarts everything as expected.

Any help/tips will be much appreciated.

Arshad

Hi Arshad,

unfortunatelly I was not able successfuly solve the problem with deep sleep on DM365 and I do not work on that project anymore. Sorry, I cannot help. I had results very similar to yours.

I think that this issue should solve some of TI FAEs as TI states that they have the best support among MCU manufacturers.

best regards
Jan

Hi Arshad,

I managed to get it working: The issue in my case was, that the CPU pll was PLL2, and when this was bypassed the ARM clock was lower than PLL1SYSCLK4. The result of this was, that any reading or writing to a peripheral clocked from PLL1SYSCLK4 (see figure 5 in SPRUFG5A) would become unreliable. Especially note that the DDR2 EMIF is clocked by PLL1SYSCLK4. My solution was to switch the CPU to PLL1 also, such that when bypassed the CPU is still clocked sufficiently higher than PLL1SYSCLK4. So I do as follows:

1. Let the CPU and DDR run from the same PLL

2. Bypass the original CPU PLL

3. Put the DDR into refresh-mode

4. Bypass the DDR PLL (which also currently clocks the CPU)

5. Poll enable DEEPSLEEP and poll

Then reverse the steps when waking up. That works for me...

Best regards,

Soren

Hi Soren

I tried the steps you followed, however I am getting stuck at bypassing the DDR PLL. I am following the same procedure as I do to bypass the CPU PLL, but it does not seem to work. The steps I follow to come out of bypass mode are:

1. Put PLL in bypass mode

2. Assert PLL reset

3. Wait for 100 (5*25 assuming 25Mhz speed) cycles

4. De-assert PLL reset

5. Carry out PLLSECCTL sequence

6. Poll PLLC1_CONFIG for pll to lock

7. Remove PLL bypass.

Could you please guide me as to how you went about taking the PLL out of bypass mode.

Thanks

Arshad

Hi Arshad,

Before disabling the PLL for the DDR, I get the code running from internal RAM, hence the routine is implemented in assembler (sleep.S). 

The steps are:

1) Put DDR in self-refresh mode

  1a) Set SRPD and LPMODEN bits in SDRCR register

  2a) Set MCLKSTOPEN bit in SDRCR register

  3a) delay

2) Disable the DDR2 LPSC (use the davinci_ddr_psc_config routine in sleep.S)

3) Disable clock to the DDR PHY, by clearing the enable bit in the appropriate PLLxDIVy register

4) Bypass and power-down the PLL

Then we enter DEEPSLEEP and start polling the SLEEPCOMPLETE bit. Re-enabling the DDR goes as follows:

1) Bring PLL out of reset

2) Program "sequence" to get PLL to lock

3) Enable the clock to DDR PHY (set the PLLxDIVy enable bit again)

4) Set the PLL "GOSET" bit and wait for lock (Using system register PLLC1_CONFIG or PLLC2_CONFIG)

5) Remove the PLL from bypass mode

6) Re-enable the DDR2 LPSC

7) Bring the DDR out of self-refresh

  7a) Clear the MCLKSTOPEN bit

  7b) clear the LPMODEN bit

At this point execution returns from internal RAM to DDR ram.

Hope that helps

Søren

Hi Soren

Thank you for you assistance. I am also running this code from internal RAM. I followed the steps you suggested to re-enable the DDR (i.e. everything except "4) Bypass and power-down the PLL" ), to ensure that the DDR can be re-enabled witthout bypassing the PLL and the code hangs at the point where I need to "1) Bring PLL out of reset".

Does this mean set or clear PLLRST? Also according to the datasheet, I am supposed to set PLLRST, wait 5us (not sure how to do that), then clear PLLRST.

And, when you say "2) Program "sequence" to get PLL to lock", do I need to set the PLLM, PREDIV and POSTDIV?

If you don't mind, could you please share the piece of code for re-enabling the DDR.

Thanks

Hi Arshad,

I've added my code below. I dont set PLLM, PREDIV or POSTDIV again, but in order to get their values to "take effect" you need to apply the "sequence" following the PLL reset (see code below).

Best regards,

Søren

wake_up:

/* Clear sleep enable */
bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
str ip, [r4, #DEEPSLEEP]

/* Clear PLL power down (power up the PLL)*/
ldr ip, [r3, #PLLCTL]
bic ip, ip, #PLLCTL_PLLPWRDN
str ip, [r3, #PLLCTL]

/* Wait at least 4 reference cycles */
ldr ip, DELAYS+(PLL_BYPASS_CYCLES*4)
3: subs ip, ip, #0x1
bne 3b

/* Put PLL in reset */
ldr ip, [r3, #PLLCTL]
orr ip, ip, #PLLCTL_PLLRST
str ip, [r3, #PLLCTL]

/* Wait at least 5 us */
ldr ip, DELAYS+(PLL_RESET_CYCLES*4)
4: subs ip, ip, #0x1
bne 4b

/* Bring PLL out of reset */
ldr ip, [r3, #PLLCTL]
bic ip, ip, #PLLCTL_PLLRST
str ip, [r3, #PLLCTL]

/* Program "sequence" to allow PLL to lock at desired frequency */
mov ip, #0x00470000 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00460000 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00400000 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00410000 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
str ip, [r3, #PLLSECCTL]

/* Enable 2x clock to DDR2 */
cmp r5, #0 /* r5 contains the PLL of the DDR, 0=>PLL1, 1=>PLL2 */
ldreq ip, [r3, #PLLDIV7]
ldrne ip, [r3, #PLLDIV3]
orr ip, ip, #PLLDIV_EN
streq ip, [r3, #PLLDIV7]
strne ip, [r3, #PLLDIV3]

/* Set the GOSET bit */
mov ip, #1
str ip, [r3, #PLLCMD]

/* Wait for PLL to lock */
cmp r5, #0
bne poll_pllc2_config
poll_pllc1_config:
ldr ip, [r4, #PLLC1_CONFIG]
and ip, ip, #PLLCx_LOCK_MASK
teq ip, #PLLCx_LOCK_MASK
bne poll_pllc1_config
b pll_locked

poll_pllc2_config:
ldr ip, [r4, #PLLC2_CONFIG]
and ip, ip, #PLLCx_LOCK_MASK
teq ip, #PLLCx_LOCK_MASK
bne poll_pllc2_config

pll_locked:

/* Remove PLL from bypass mode */
ldr ip, [r3, #PLLCTL]
bic ip, ip, #PLLCTL_PLLENSRC
orr ip, ip, #PLLCTL_PLLEN
str ip, [r3, #PLLCTL]

/* Enable DDR2 LPSC */
mov r7, r0
mov r0, #0x3
bl davinci_ddr_psc_config
mov r0, r7

/* clear MCLKSTOPEN */
ldr ip, [r0, #DDR2_SDRCR_OFFSET]
bic ip, ip, #DDR2_MCLKSTOPEN_BIT
str ip, [r0, #DDR2_SDRCR_OFFSET]

/* clear LPMODEN to stop self-refresh */
ldr ip, [r0, #DDR2_SDRCR_OFFSET]
bic ip, ip, #DDR2_LPMODEN_BIT
str ip, [r0, #DDR2_SDRCR_OFFSET]

/* Restore registers and return */
ldmfd sp!, {r0-r12, pc}

Hi Soren

The code I have is very similar to yours, except that I do not check if I am using PLL1 or PLL2 for the DDR, since I know I am using PLL1. Also, your delays are different (DELAYS is undefined for me).

You mention that /* r5 contains the PLL of the DDR, 0=>PLL1, 1=>PLL2 */, but from the rest of the code it seems that r3 contains the base address for the DDR PLL.

As I mentioned in the post before this, that I am not putting the DDR into bypass mode, so I can figure out if the wake up procedure works. If you where to do the same, does your code still work.

Is it possible for you to attach your sleep.S and pm.c files.

I appreciate your assistance.

Thanks

Arshad

Hi Soren

I managed to get it to work. It turns out, I needed a delay after returning from internal RAM. Once again thanks alot for your assistance, I really appreciate it :).

Regards

Arshad

Hello Arshad,

I have been experiencing similar problems with Deepsleep. It seems that you have found a solution. Would you be able to potentially post this solution, or describe in detail each of the steps involved in the solution. At the moment, I have the following steps:

• Switch the CPU PLL to bypass - writes 0s to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL2)
• Wait 4 cycles for Bypass
• Power down the CPU PLL - writes 1 to PLLCTL_PLLPWRDN
• Configure sleep count in the deep sleep register - writes 128 into the deepsleep register
• call sleep.S file - goes into SRAM
  
  • store all registers
  • call arm926_flush_kern_cache_all
  • load r0 - r4 with the information passed in from pdata
  • Put DDR into self-refresh - write 0 to SRPD and 1 to LPMODEN in SDRCR
  • Stop MCLK - write 1 to MCLKSTOPEN in SDRCR
  • wait 4096 cycles
  • Disable DDR2 LPSC
  • Put DDR into bypass mode - write 0 pllctl_pllensrc and pllctl_pllen (PLL1)
  • wait 4 cycles for bypass
  • Put PLL into reset - write 1 to PLLCTL_PLLRST (PLL1)
  • Disable clock to DDR PHY - write 0 to PLLDIV_EN
  • Power down DDR PLL - write 1 to PLLCTL_PLLPWRDN (PLL1)
  • Go to deep sleep - write 1 to DEEPSLEEP_SPEELENABLE_BIT
  • Stay in loop polling DEEPSLEEP_SLEEPCOMPLETE_BIT
    
    • Transition GIO0 from high to low, wait more than 500ns, then low to high
  • Clear sleep enable - write 0 to DEEPSLEEP_SLEEPENABLE_BIT
  • Clear PLL power down - write 0 to PLLCTL_PLLPWRDN
  • Put PLL into bypass mode - write 0 to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL1)
  • Put PLL into reset - write 1 to PLLCTL_PLLRST (PLL1)
  • wait 125 cycles for reset to take place
  • Take PLL out of reset - write 0 to PLLCTL_PLLRST (PLL1)
  • Start DDR PHY - write 1 to PLLDIV_EN
  • Wait 600 cycles for PLL to lock
  • Remove PLL from bypass - write 0 to PLLCTL_PLLENSRC and 1 to PLLCTL_PLLEN (PLL1)
  • Enable DDR2 LPSC
  • Enable MCLK - write 0 to MCLKSTOPEN
  • Bring DDR2 out of self-refresh - write 0 to LPMODEEN and 1 to SRPD
  • Restore registers and return
• Remove CPU PLL from power down - write 0 to PLLCTL_PLLPWRDN (PLL2)
• Put CPU PLL into bypass - write 0 to PLLCTL_PLLENSRC (PLL2)
• wait 4 clock cycles
• Put CPU PLL in reset - write 1 to PLLCTL_PLLRST (PLL2)
• wait 25 clock cycles
• Bring CPU PLL out of reset - write 0 to PLLCTL_PLLRST (PLL2)
• PLLSECCTL pattern (TENABLE, TENABLEDIV, TINITZ): (1,1,1); (1,1,0); (0,0,0); (0,0,1)
• POLL LOCK1, LOCK2, LOCK3 of the system module PLLC2_CONFIG registers until all 1s
• Remove PLL from bypass - write 0 to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL2)
• wait 4 clock cycles
• Return to normal functionality

This seems to either hang up after trying to return to normal functionality or after I try to put the CPU PLL into bypass mode after powering the CPU PLL back up.

Any information that you could supply would be greatly appreciated.

Thanks

Hi James,

You will notice in one of the posts before this, where Soren mentioned:

"I managed to get it working: The issue in my case was, that the CPU pll was PLL2, and when this was bypassed the ARM clock was lower than PLL1SYSCLK4. The result of this was, that any reading or writing to a peripheral clocked from PLL1SYSCLK4 (see figure 5 in SPRUFG5A) would become unreliable. Especially note that the DDR2 EMIF is clocked by PLL1SYSCLK4. My solution was to switch the CPU to PLL1 also, such that when bypassed the CPU is still clocked sufficiently higher than PLL1SYSCLK4."

So before you bypass the CPU PLL, let the CPU and DDR run from the same PLL, by clearing the ARMCLKS bit in the PERI_CLKCTL register of the system control module.

• Switch the CPU PLL to bypass - writes 0s to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL2)
• Wait 4 cycles for Bypass
• Power down the CPU PLL - writes 1 to PLLCTL_PLLPWRDN
• Configure sleep count in the deep sleep register - writes 128 into the deepsleep register

I used a sleepcount of 4096, to ensure that the osillator is stable before enabling clocks.

• call sleep.S file - goes into SRAM

• store all registers
• call arm926_flush_kern_cache_all

You make no mention of branching to ip (blx   ip) between the following steps. I noticed that if that line (blx   ip) is included, the processor hangs, so I commented it out.

• load r0 - r4 with the information passed in from pdata
• Put DDR into self-refresh - write 0 to SRPD and 1 to LPMODEN in SDRCR
• Stop MCLK - write 1 to MCLKSTOPEN in SDRCR
• wait 4096 cycles

I actually wait 1000 cycles. I don't see any harm in waiting longer, but I do know that if you want to load a value greater than 1000 to ip, you cannot use the mv command.

• Disable DDR2 LPSC

I noticed that you disable the clock to DDR PHY (PLLDIV7) after putting the DDR into bypass mode. I'm not sure if that is an issue, but I do it before.

• Put DDR into bypass mode - write 0 pllctl_pllensrc and pllctl_pllen (PLL1)
• wait 4 cycles for bypass
• Put PLL into reset - write 1 to PLLCTL_PLLRST (PLL1)

Also, I don't see the need to put the PLL into reset.

• Disable clock to DDR PHY - write 0 to PLLDIV_EN
• Power down DDR PLL - write 1 to PLLCTL_PLLPWRDN (PLL1)
• Go to deep sleep - write 1 to DEEPSLEEP_SPEELENABLE_BIT
• Stay in loop polling DEEPSLEEP_SLEEPCOMPLETE_BIT
  
  • Transition GIO0 from high to low, wait more than 500ns, then low to high
• Clear sleep enable - write 0 to DEEPSLEEP_SLEEPENABLE_BIT
• Clear PLL power down - write 0 to PLLCTL_PLLPWRDN

After waking up and clearing PLL power down, I wait 4 clock cycles.

• Put PLL into bypass mode - write 0 to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL1)

There is no need to put the PLL back into bypass mode.

• Put PLL into reset - write 1 to PLLCTL_PLLRST (PLL1)
• wait 125 cycles for reset to take place
• Take PLL out of reset - write 0 to PLLCTL_PLLRST (PLL1)

/* Program "sequence" to allow PLL to lock at desired frequency */
mov ip, #0x00470000 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00460000 /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00400000 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
str ip, [r3, #PLLSECCTL]
mov ip, #0x00410000 /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
str ip, [r3, #PLLSECCTL]

/* Set the GOSET bit */
mov ip, #1
str ip, [r3, #PLLCMD]

Wait for PLL lock

Remove PLL from bypass

• Start DDR PHY - write 1 to PLLDIV_EN
• Wait 600 cycles for PLL to lock
• Remove PLL from bypass - write 0 to PLLCTL_PLLENSRC and 1 to PLLCTL_PLLEN (PLL1)
• Enable DDR2 LPSC
• Enable MCLK - write 0 to MCLKSTOPEN

Poll SDRSTAT to check that MCLK is started

• Bring DDR2 out of self-refresh - write 0 to LPMODEEN and 1 to SRPD

At this point I actually wait 2000 cycles.

• Restore registers and return

I also wait here for 100 microseconds.

• Remove CPU PLL from power down - write 0 to PLLCTL_PLLPWRDN (PLL2)
• Put CPU PLL into bypass - write 0 to PLLCTL_PLLENSRC (PLL2)

No need to put PLL into bypass

• wait 4 clock cycles
• Put CPU PLL in reset - write 1 to PLLCTL_PLLRST (PLL2)
• wait 25 clock cycles
• Bring CPU PLL out of reset - write 0 to PLLCTL_PLLRST (PLL2)
• PLLSECCTL pattern (TENABLE, TENABLEDIV, TINITZ): (1,1,1); (1,1,0); (0,0,0); (0,0,1)

Set the GOSET bit

• POLL LOCK1, LOCK2, LOCK3 of the system module PLLC2_CONFIG registers until all 1s
• Remove PLL from bypass - write 0 to PLLCTL_PLLENSRC and PLLCTL_PLLEN (PLL2)
• wait 4 clock cycles

Switch clock source of CPU back to PLL2

• Return to normal functionality

This seems to either hang up after trying to return to normal functionality or after I try to put the CPU PLL into bypass mode after powering the CPU PLL back up.

I suggest that you work from the outside in, to figure out where exactly your problem lies. So, as an initial test, comment out the code that puts the unit into SRAM (davinci_sram_suspend(pdata);) and check that you can successfully put the CPU PLL into bypass and successfully take it out of bypass.

Hope this helps

Regards

Arshad

Hey Guys,

In connection with deep sleep for the dm365, I am having an issue with vpfe_suspend(). Originally I had no support for vpfe_suspend, so I used part of the following patch http://osdir.com/ml/linux-media/2009-11/msg00807.html which is actually for the dm644x. I did not use the ccdc_save_context() and ccdc_restore_context() functions, as they seemed to not do anything (i.e. after ccdc_save_context, I printed the registers and they were all zero). So regardless of whether I used the ccdc_save/restore_context functions, I still experienced a different issue.

 The issue is, when vpfe_suspend is called, it calls vpfe_disable_clock(vpfe_dev), which calls clk_disable(vpfe_dev->clks[i]). At this point, where the clock is being disabled, the processor sometimes hangs. Because the issue is not consistent, it makes it more difficult to debug and hence fix.

 Any help will be much appreciated.

Regards

Arshad

Hi Arshad,

It seems like I'm not able to put it to sleep and then come back out. Once it returns to the dram it just stops. Adding the 100us delay upon return does not seem to fix it. I can execute some assembly code lines to print a b to the terminal, which tells me that it come back out of sram, but I cannot get my next character c to print following the 100us delay. If I don't print the b, then no character tells me that I have returned (it still does not print the c after the delay).

This problem goes away if I do not go to sleep at all (no deepsleep state machine steps), but if I do sleep, then it will not execute again. I'm not sure what is happening in this case.

Thanks for the help in advanced