UART - parity Error detection issue

Tejas,

I am not sure that this test should necessarily trigger a parity error.  How are you configuring the even and odd parity, and what is the UART_LCR register set to in both cases?  For example, if the Line Control Register PEN=0, then the UART neither generates a parity bit for outgoing characters nor checks the incoming characters for their parity.

Regards,
Gina 

Hi Gina,

This is how I configure parity :

UART_WRITE(OFS_LINE_CONTROL, \
UART_READ(OFS_LINE_CONTROL) | \
LCR_PARITY_EN);
if(parity) {
UART_WRITE(OFS_LINE_CONTROL, \
UART_READ(OFS_LINE_CONTROL) | \
LCR_PARITY_TYPE);
} else {
UART_WRITE(OFS_LINE_CONTROL, \
UART_READ(OFS_LINE_CONTROL) & \
(~(LCR_PARITY_TYPE)));
}

Tejas,

How are LCR_PARITY_EN, LCR_PARITY_TYPE, and parity defined?  I assume that LCR_PARITY_EN is (1 << 3), but is LCR_PARITY_TYPE is (1 << 4) or (1 << 5)?  See the LCR register definition in Table 23-184 of the OMAP4 TRM.  (The public TRMs are available here: http://www.ti.com/general/docs/wtbu/wtbudocumentcenter.tsp?templateId=6123&navigationId=12037#65)  This affects whether the parity is checked to be even/odd or whether it must be the same for transmitted/received.

Regards,
Gina

Hi Gina,

Thanks for your prompt reply,

LCR_PARITY_EN is (1 << 3) and LCR_PARITY_TYPE is (1 << 4).

and on another board this same combination generates parity bit On. Register description in both the board were same. In PANDA-4430 i dont see parity bit on. 

Let me know in case you need any further detail about my code.

Thanks,

Tejas

Tejas,

I assume that PARITY_TYPE_2 (LCR bit 5) is set to 0, meaning that you are forcing to either odd parity or even parity?  Earlier you mentioned "I dont get parity error bit enable in  LINE_STATUS_REGISTER."  But now you mean that you also don't get parity bit on in the UART data frame?  If that is the case, can you do a quick test with LCR bit 5 set to 1, and LCD bit 4 set to 0; this will force the parity bit to 1.  Can you read out the value for the UART_LCR right before you don't see the parity bit on in the UART frame?

Regards,
Gina 

Yes PARITY_TYPE_2 (LCR bit 5) is set to 0.

Whatever parity I configure I can see that the parity bit ( no issue with parity bit configuration) is actually configured (odd or even) in UART_LCR register. I have also practically seen it changing the minicom's parity where if I match parity with board's UART parity I am getting proper logs, not otherwise.

But in this test flow as follows :

 loopbackmode, setting odd parity , sending the byte, changing the parity to even, receive the byte ,  and then I check UART_LSR , where I should get parity error bit on. This is not happening.

Gina,

Many thanks for replying me regularly. 

If what you are saying is the case then same test should not work for other board as well. But it does. We are running same test on other athroes board and we are getting it done successfully.

Thanks,

Tejas

Tejas,

Unfortunately we don't have a good explanation for this.  UART sets the parity for RX and TX at the same time, so there shouldn't be a parity error in loopback mode.  Are you following the exact same procedure as on your other board?  What are the full values for the LCR and LSR before and after each transaction?

Regards,
Gina