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ISS HW interface question



Dear TI Tech Support,

I have a hardware interface related question on DM8148. Your kind answer will be highly appreciated.

In our video camera system, we use an FPGA to do ISP (image signal processing) and a DM8148 to do video analysis. The interface between the FPGA and DM8148 is generic YCbCr 16-bit parallel. My question to you is: Does the DM8148 expect the blanking intervals b/w successive HSYNCs as fixed or can they vary? How much would the DM8148 be able to tolerate these variations? If any of your documents mentioned about this please point it out for me.

Thanks a lot,

Ricky