How to check memory cache status and speed on DSP of TI Davinci 8168 SoC?

chao wen

Other Parts Discussed in Thread: SYSBIOS

Hi, Ti Expertsof 8168,

I am migrating algorithm to the DSP core on RDK2.0 for 8168evm board. The code migration is successful, but the speed is much lower than my expect: Previous using c6run to use DSP core, the test on the board shows it can run at 3 fps, but on MCFW framework it gets only 0.5 fps, so I think there is something I missed.

So I have some question hope you expert could help me:

1 How to got a local time stamp on DSP? Currently I got the timestamp from other core, which is not precise to determine the algorithm's time consuming.

2 How to check or change DSP's cache status for the memory? The algorithm needs about 300ms for each frame, But from document it seems the SR2, frame buffer region have no cache enabled. What I need is , I hope I can invalidate the cache on the frame memory, and then in the following procedure use cache. Also, because the system heap for DSP is too small, I cut about 60M memory from other section to DSP system heap, and modified the configuration file. It ran OK, but I am not sure if the DSP/bios6 will enable cache on system heap automatically, resulting poor performance. Searched the configuration file, it seems not a obvious line specifying it.

Hope you can give some advice or speed reason assess for it, the speed is critical for the platform competitive advance.

My platform:

8168evm+ddr3

DVR_RDK2.0

algorithm speed with c6run on dsp: 300ms/frame, with mcfw alglink on dsp: 2000ms/frame, for each frame all Y data in memory is accessed.

over 13 years ago

0 chao wen over 13 years ago

Prodigy 210 points

Hi, any one could help me?

0 Marko Shink over 13 years ago in reply to chao wen

Genius 3475 points

Hi,
I'm using DM8148, but i guess it's the same.
Enable/disable cache by set bits in MAR registers in : mcfw\src_bios6\cfg\ti816x\FC_RMAN_IRES_c6xdsp.cfg
Bits that are set enables cache on a specific 16MB memory region.

You can find MAR regions in sprufk5a.pdf (Table 4-21. Memory Attribute Registers)
I have the following settings, but it depends on your DSP memory configuration in "config_dsp.bld":
var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
Cache.MAR0_31    = 0x00000000;
Cache.MAR32_63   = 0x00000000;
Cache.MAR64_95   = 0x00000000;
Cache.MAR96_127 = 0x00000000;
Cache.MAR128_159 = 0x0000FF00;
Cache.MAR160_191 = 0x00FF0000;
Cache.MAR192_223 = 0x00000000;
Cache.MAR224_255 = 0x00000000;

-----
I use Timestamp_get32 for timestamps.

-----
Regards.

0 chao wen over 13 years ago in reply to Marko Shink

Prodigy 210 points

Thanks, that is what I am looking for, modified but not tested it on board. Do you know how to check it is correctly set in DSP program, I am a bit worry about whether it would be used after build scripts ran. Also there is a section in cfg/SYSYLINK_common.cfg:

SharedRegion.setEntryMeta( 0,
    {
      base:        sr0MemSection.base,
      len:         sr0MemSection.len,
      name:        sr0MemSection.name,
      isValid:     true,
      ownerProcId: srOwnerProcId,
      cacheEnable: false,
      cacheLineSize: 128,
      createHeap: true
    }
);

Not sure if these sections would affect/make trouble to the final cache setting result on DSP.

0 Marko Shink over 13 years ago in reply to chao wen

Genius 3475 points

Hi,
It seems that all shared regions have its purpose in RDK, and are already used by other code and processors (ARM, M3).
So it's probably not OK to change cache status of shared regions, since you may effect other part of RDK programs.
You could use SR1 , which already has cache enabled, and set MAR bits for SR1 - if you really need to put your data on a shared region.
But it's probably better to put your data on local "DSP data" section and enable cache (by setting MAR bits), and maybe make "DSP data" section larger (and TILER smaller).
It is in file "config_dsp.bld" :
...
| 2MB          | DSP code
+--------------+
| 10MB         | DSP data
....
DSP_CODE_SIZE     = 2*MB;
DSP_DATA_SIZE = 10*MB;
------------------
Based on those values you can calculate DSP_DATA_ADDR which is
DSP_DATA_ADDR              = DSP_CODE_ADDR              + DSP_CODE_SIZE;

And this DSP_DATA_ADDR is the address where you have to set MAR bits.
If you send your "config_dsp.bld" you are using, i can tell you MAR settings.
Or you can tell the specific section where you want to put variable with pragmas:

Top of your dspcodefile.c:
#pragma DATA_SECTION(MyArray, ".dataMemory")
#pragma DATA_ALIGN(MyArray, 128)
static unsigned char MyArray[1024*30];
------------
"BIOS_c6xdsp.cfg" file:
Program.sectMap[".dataMemory"] = "DDR3_DSP";
------------
"config_dsp.bld" file
        ["DSP_DATA_MEM", {
            comment : "DDR3_DSP",
            name    : "DDR3_DSP",
            base    : DSP_DATA_ADDR,
            len     : DSP_DATA_SIZE
        }],
------------

0 chao wen over 13 years ago in reply to Marko Shink

Prodigy 210 points

ah, I tested it on board and got a incredible performance improvement, many thank!

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How to check memory cache status and speed on DSP of TI Davinci 8168 SoC?