[DM36x] clock leveling for NAND flash

Hayden Kim

Genius 15580 points

There is a question about DM36x NAND interface.

Is it possible to do clock leveling (manually) for NAND flash?

If possible, what register can we control?

over 13 years ago

0 Renjith Thomas over 13 years ago

Guru 31670 points

You have to control the function clock to the EMIF using PLL1->SYSCLK4. You can change the divisors values in PLL1->PLLDIV4 register for the same.

0 Hayden Kim over 13 years ago in reply to Renjith Thomas

TI__Genius 15580 points

Here is another questions about changing the divisor value.

Is it possible to change PLLC1->PLLDIV4 register value anytime during working?

Or, is there specific timing to do setting the divisor value?

If there is specific timing, when?

0 Renjith Thomas over 13 years ago in reply to Hayden Kim

Guru 31670 points

I believe NAND will fail if the clock is changed at run time, as the NAND and other related peripherals has to be reconfigured according to the new clock value. Also the NAND timings are calculated according to the FCLK cycles. This will change if you change the EMIF function clock frequency.

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[DM36x] clock leveling for NAND flash