HI,
1.In EVM Schematic DSP smart reflex section DSP6678 Pins are M24-VCL & M23-VD are connected to PM bus through level shifter.But as per DSP6678 datasheet these pins are reserved pins & they are unconnected.
we are going to use Same power supply section in EVM schematic.Can we left pins M24 &M23floating?.
2.In Power supply section CVDD & VCC1V0 are supplied by UCD7242 Synchronous buck power driver controlled by UCD9222.
UCD7242 efficiency,load characteristics etc are given at room temperature.Our product will fit into locomotive where ambient temperature is 55 to 65°C.We want to know deration at 55°C ambient and 85°C junction temperature.If this device is not suitable then suggest alternate part which can be interfaced with UCD9222.
3.In UCD7242 CVDD & VCC1V0 are having Tantalum capacitors at output, can we use electrolytic capacitors instead of tantalum.
4.In UCD9222 PC based Graphical User Interface available.
Can we use directly UCD9222 with PM bus interface with FPGA without PC application?.
Provide PC graphical user interface data can be useful for time domain simulations.
5.We are removing AMC interface in our schematic.Ethernet interface we are using same.
SGMII1 is used for ethernet we are going to use same as per EVM schematic.
SGMII0 is used for AMC, As per hardware design guidelines document unused SGMII RXP RXN TXP TXN should be left floating.Can we left floating or we needs to pull down or pullup these pins?.
6.We are not going to use SRIO, PCIE & HYPERLINK interfaces.Can we left floating or we needs to pull down or pullup these pins?.
7.In DSP clock section we are retaining CORECLOCK,DDRCLOCK(We are using DDR3 section),PASS clock(ethernet network accelerator) & SRIOSGMII clock.
As we are not going to use PCIE & Hyperlink we are removing PCIE clock & Hyperlink clock.We have tied
PCIE & Hyperlink CLKP to CVDD & CLKN to ground as per hardware design guidelines is it ok?.
8.In Clock generator section CDCE6205 each clock generator is capable of generating 4 different clocks,
Since we are not using PCIE & Hyperlink clock we require only four clocks can we connect 4 clocks to one Clock generator CDCE62005 with crystal 25MHZ.
HYPERLINK & SGMII clock are at 312.5Mhz as per schematic, reference clock for CDCE62005 for these clocks are 100Mhz derived from other clock generator Output.
Is there any jittering issues with reference clock 25Mhz and required clock 312.5Mhz.
10.DSP6678 Code downloading into non volatile memory SPI NAND flash or I2C EEPROM.
At poweron as per bootpin settings Code shall be copied from SPI NAND Flash or I2C EEPROM, But for the first time how we have to dump the code into non volatile memory?
Through emulator can we write the code into non volatile memory. Please share options available with other users.
Thanks & Regards,
Prasad
