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PCIe communication between c6670 and Kintex7 FPGA

andresf.atehortua
Prodigy 85 points
Other Parts Discussed in Thread: TMDXEVMPCI

Hello TI community,

Currently I'm working on a project where a fast communication between a c6670 DSP and the Kintex 7 FPGA must be carried out. Our group decided to do this communication using the PCIe protocol since both EVM boardshave the PCIe interface.

So we basically designed a PCB to connect the boards but we encountered the communication wasn't working. After some reading we discovered the Kintex 7 EVM needs an external reference clock of 100MHz to get the PCIe communication work properly. Unfortunately the c6670 EVM does not provide this clock because for some reason I still don't understand, the refclk it has only works as an input and it does not have any clk output that can supply this reference clock needed by the FPGA. So I have some questions:

  1. Is it necessary to use a SSC Clock reference to make a PCIe communication?
  2. Can one use a simple 100MHz clock as a reference for both EVMs?
  3. Beside the clock and the DC-blocking capacitors, do I need another IC for my communication to work properly?
Hope you guys can give me a hand on this matter, since without this communication my project could literally go to the trash.
Regards,
Andrés
  • 0
    TI__Mastermind 46460 points

    Andres,

    PCIe operates with both common clocking and separate clocks.  If you operate the root complex and the endpoint on separate clocks, then they both must be narrow-band clocks like the one on the EVM.  If you want to use a Spread Spectrum Clock then both the root complex and the endpoint must be driven from the same clock.  When you connect 2 EVMs over our CI2EVMBOC (available from the eStore), they operate using separate, local clocks.  When you insert an EVM into an ATX PC using the TMDXEVMPCI (also available from the eStore), the SSC clock from the motherboard is selected.  I recommend that you experiment with 2 EVMs and a CI2EVMBOC and our PCIe examples in the MCSDK to gain operational understanding.

    I will also answer your questions directly:

    1.  SSC clocking is not a requirement

    2.  A simple 100MHz clock reference is acceptable.  The 2 EVMs can use separate clocks or a common clock.  Please note that this needs to be a very low jitter clock since PCIe is a high performance interface.  The KeyStone Hardware Design Guide provides requirements.

    3.  No other circuitry is needed.  Once the clocks are correct, the PCIe ports need to be cross connected using DC-blocking capacitors.  Note that these are on the RX pins on the C6670 EVM and they may be on the TX pins on the FPGA board.  They are needed on all links.

    Tom

     

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 85 points

    Hello Tom,

    Thank you very much for your answers, I must say it is a relief to know we don't have to use a SSC. I'll then get to work and carry out this comm, will let you know the results.

    Andrés